| Message ID | 20250306-videocc-pll-multi-pd-voting-v2-0-0cd00612bc0e@quicinc.com |
|---|---|
| Headers | show |
| Series | clk: qcom: Add support to attach multiple power domains in cc probe | expand |
On Thu, Mar 06, 2025 at 02:25:35PM +0530, Jagadeesh Kona wrote: > Add support for runtime power management, PLL configuration and enabling > critical clocks in qcom_cc_really_probe() to commonize the clock > controller probe. Please split this into two commits: one for the runtime PM and another one for clock configuration, because ... > > The runtime power management is not required for all clock controllers, > hence handle the rpm based on use_rpm flag in clock controller descriptor. > Also the power domains need to be kept enabled during pll configuration, > hence attach all required power domains prior to calling get_sync() on the > device. > > Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> > --- > drivers/clk/qcom/common.c | 45 ++++++++++++++++++++++++++++++++++++--------- > drivers/clk/qcom/common.h | 16 ++++++++++++++++ > 2 files changed, 52 insertions(+), 9 deletions(-) [...] > + > + for (i = 0; i < desc->num_plls; i++) > + qcom_cc_clk_pll_configure(desc->plls[i], regmap); > + > + for (i = 0 ; i < desc->num_clks_cfg; i++) > + regmap_update_bits(regmap, clks_cfg[i].offset, > + clks_cfg[i].mask, clks_cfg[i].mask); > + ... just calling regmap_update_bits() looks like a step backwards. In the past several years we got several sensible wrappers and helpers. I suggest having a callback instead of a fixed 'update bits' table. > reset = &cc->reset; > reset->rcdev.of_node = dev->of_node; > reset->rcdev.ops = &qcom_reset_ops; The RPM part is fine with me.
In some of the recent chipsets, PLLs require more than one power domain to be kept ON to configure the PLL. But the current code doesn't enable all the required power domains while configuring the PLLs, this leads to functional issues due to suboptimal settings of PLLs. To address this, add support for handling runtime power management, configuring plls and enabling critical clocks from qcom_cc_really_probe. The clock controller can specify PLLs, critical clocks, and runtime PM requirements in the descriptor data. The code in qcom_cc_really_probe() ensures all necessary power domains are enabled before configuring PLLs or critical clocks. This series updates SM8450 & SM8550 videocc drivers to handle rpm, configure PLLs and enable critical clocks from within qcom_cc_really_probe() using above support, so video PLLs are configured properly. This series fixes the below warning reported in SM8550 venus testing due to video_cc_pll0 not properly getting configured during videocc probe [ 46.535132] Lucid PLL latch failed. Output may be unstable! The patch adding support to configure the PLLs from common code is picked from below series and updated it. https://lore.kernel.org/all/20250113-support-pll-reconfigure-v1-0-1fae6bc1062d@quicinc.com/ Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> --- Changes in v2: - Added support to handle rpm, PLL configuration and enable critical clocks from qcom_cc_really_probe() in common code as per v1 commments from Bryan, Konrad and Dmitry - Added patches to configure PLLs from common code - Updated the SM8450, SM8550 videocc patches to use the newly added support to handle rpm, configure PLLs from common code - Split the DT change for each target separately as per Dmitry comments - Added R-By and A-By tags received on v1 - Link to v1: https://lore.kernel.org/r/20250218-videocc-pll-multi-pd-voting-v1-0-cfe6289ea29b@quicinc.com --- Jagadeesh Kona (7): dt-bindings: clock: qcom,sm8450-videocc: Add MXC power domain clk: qcom: common: Manage rpm, configure PLLs & AON clks in really probe clk: qcom: videocc-sm8450: Move PLL & clk configuration to really probe clk: qcom: videocc-sm8550: Move PLL & clk configuration to really probe arm64: dts: qcom: Add MXC power domain to videocc node on SM8450 arm64: dts: qcom: Add MXC power domain to videocc node on SM8550 arm64: dts: qcom: Add MXC power domain to videocc node on SM8650 Taniya Das (1): clk: qcom: common: Add support to configure PLL .../bindings/clock/qcom,sm8450-videocc.yaml | 9 +- arch/arm64/boot/dts/qcom/sm8450.dtsi | 3 +- arch/arm64/boot/dts/qcom/sm8550.dtsi | 3 +- arch/arm64/boot/dts/qcom/sm8650.dtsi | 3 +- drivers/clk/qcom/clk-alpha-pll.h | 2 + drivers/clk/qcom/common.c | 100 +++++++++++++++++++-- drivers/clk/qcom/common.h | 17 ++++ drivers/clk/qcom/videocc-sm8450.c | 49 +++++----- drivers/clk/qcom/videocc-sm8550.c | 50 +++++------ 9 files changed, 167 insertions(+), 69 deletions(-) --- base-commit: e5d3fd687aac5eceb1721fa92b9f49afcf4c3717 change-id: 20250218-videocc-pll-multi-pd-voting-d614dce910e7 Best regards,