diff mbox series

[v4,137/163] tcg/ppc: Implement add/sub carry opcodes

Message ID 20250415192515.232910-138-richard.henderson@linaro.org
State New
Headers show
Series tcg: Convert to TCGOutOp structures | expand

Commit Message

Richard Henderson April 15, 2025, 7:24 p.m. UTC 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/ppc/tcg-target-con-set.h |   3 +
 tcg/ppc/tcg-target-con-str.h |   1 +
 tcg/ppc/tcg-target.c.inc     | 167 ++++++++++++++++++++++++++++++-----
 3 files changed, 150 insertions(+), 21 deletions(-)

Comments

Pierrick Bouvier April 16, 2025, 7:14 p.m. UTC | #1 
On 4/15/25 12:24, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>   tcg/ppc/tcg-target-con-set.h |   3 +
>   tcg/ppc/tcg-target-con-str.h |   1 +
>   tcg/ppc/tcg-target.c.inc     | 167 ++++++++++++++++++++++++++++++-----
>   3 files changed, 150 insertions(+), 21 deletions(-)
> 
> diff --git a/tcg/ppc/tcg-target-con-set.h b/tcg/ppc/tcg-target-con-set.h
> index 14cd217287..9ea26c40ae 100644
> --- a/tcg/ppc/tcg-target-con-set.h
> +++ b/tcg/ppc/tcg-target-con-set.h
> @@ -29,7 +29,10 @@ C_O1_I2(r, r, rC)
>   C_O1_I2(r, r, rI)
>   C_O1_I2(r, r, rT)
>   C_O1_I2(r, r, rU)
> +C_O1_I2(r, r, rZM)
>   C_O1_I2(r, r, rZW)
> +C_O1_I2(r, rI, rN)
> +C_O1_I2(r, rZM, rZM)
>   C_O1_I2(v, v, v)
>   C_O1_I3(v, v, v, v)
>   C_O1_I4(v, v, v, vZM, v)
> diff --git a/tcg/ppc/tcg-target-con-str.h b/tcg/ppc/tcg-target-con-str.h
> index 16b687216e..faf92da47f 100644
> --- a/tcg/ppc/tcg-target-con-str.h
> +++ b/tcg/ppc/tcg-target-con-str.h
> @@ -19,6 +19,7 @@ REGS('v', ALL_VECTOR_REGS)
>   CONST('C', TCG_CT_CONST_CMP)
>   CONST('I', TCG_CT_CONST_S16)
>   CONST('M', TCG_CT_CONST_MONE)
> +CONST('N', TCG_CT_CONST_N16)
>   CONST('T', TCG_CT_CONST_S32)
>   CONST('U', TCG_CT_CONST_U32)
>   CONST('W', TCG_CT_CONST_WSZ)
> diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
> index 5b04655f3b..0b151db0e4 100644
> --- a/tcg/ppc/tcg-target.c.inc
> +++ b/tcg/ppc/tcg-target.c.inc
> @@ -89,14 +89,15 @@
>   /* Shorthand for size of a register.  */
>   #define SZR  (TCG_TARGET_REG_BITS / 8)
>   
> -#define TCG_CT_CONST_S16  0x100
> -#define TCG_CT_CONST_U16  0x200
> -#define TCG_CT_CONST_S32  0x400
> -#define TCG_CT_CONST_U32  0x800
> -#define TCG_CT_CONST_ZERO 0x1000
> -#define TCG_CT_CONST_MONE 0x2000
> -#define TCG_CT_CONST_WSZ  0x4000
> -#define TCG_CT_CONST_CMP  0x8000
> +#define TCG_CT_CONST_S16     0x00100
> +#define TCG_CT_CONST_U16     0x00200
> +#define TCG_CT_CONST_N16     0x00400
> +#define TCG_CT_CONST_S32     0x00800
> +#define TCG_CT_CONST_U32     0x01000
> +#define TCG_CT_CONST_ZERO    0x02000
> +#define TCG_CT_CONST_MONE    0x04000
> +#define TCG_CT_CONST_WSZ     0x08000
> +#define TCG_CT_CONST_CMP     0x10000
>   
>   #define ALL_GENERAL_REGS  0xffffffffu
>   #define ALL_VECTOR_REGS   0xffffffff00000000ull
> @@ -342,6 +343,9 @@ static bool tcg_target_const_match(int64_t sval, int ct,
>       if ((ct & TCG_CT_CONST_U16) && uval == (uint16_t)uval) {
>           return 1;
>       }
> +    if ((ct & TCG_CT_CONST_N16) && -sval == (int16_t)-sval) {
> +        return 1;
> +    }
>       if ((ct & TCG_CT_CONST_S32) && sval == (int32_t)sval) {
>           return 1;
>       }
> @@ -2863,21 +2867,69 @@ static const TCGOutOpBinary outop_add = {
>       .out_rri = tgen_addi,
>   };
>   
> +static void tgen_addco_rrr(TCGContext *s, TCGType type,
> +                           TCGReg a0, TCGReg a1, TCGReg a2)
> +{
> +    tcg_out32(s, ADDC | TAB(a0, a1, a2));
> +}
> +
> +static void tgen_addco_rri(TCGContext *s, TCGType type,
> +                           TCGReg a0, TCGReg a1, tcg_target_long a2)
> +{
> +    tcg_out32(s, ADDIC | TAI(a0, a1, a2));
> +}
> +
> +static TCGConstraintSetIndex cset_addco(TCGType type, unsigned flags)
> +{
> +    /*
> +     * Note that the CA bit is defined based on the word size of the
> +     * environment.  So in 64-bit mode it's always carry-out of bit 63.
> +     * The fallback code using deposit works just as well for TCG_TYPE_I32.
> +     */
> +    return type == TCG_TYPE_REG ? C_O1_I2(r, r, rI) : C_NotImplemented;
> +}
> +
>   static const TCGOutOpBinary outop_addco = {
> -    .base.static_constraint = C_NotImplemented,
> +    .base.static_constraint = C_Dynamic,
> +    .base.dynamic_constraint = cset_addco,
> +    .out_rrr = tgen_addco_rrr,
> +    .out_rri = tgen_addco_rri,
> +};
> +
> +static void tgen_addcio_rrr(TCGContext *s, TCGType type,
> +                            TCGReg a0, TCGReg a1, TCGReg a2)
> +{
> +    tcg_out32(s, ADDE | TAB(a0, a1, a2));
> +}
> +
> +static void tgen_addcio_rri(TCGContext *s, TCGType type,
> +                            TCGReg a0, TCGReg a1, tcg_target_long a2)
> +{
> +    tcg_out32(s, (a2 ? ADDME : ADDZE) | RT(a0) | RA(a1));
> +}
> +
> +static TCGConstraintSetIndex cset_addcio(TCGType type, unsigned flags)
> +{
> +    return type == TCG_TYPE_REG ? C_O1_I2(r, r, rZM) : C_NotImplemented;
> +}
> +
> +static const TCGOutOpBinary outop_addcio = {
> +    .base.static_constraint = C_Dynamic,
> +    .base.dynamic_constraint = cset_addcio,
> +    .out_rrr = tgen_addcio_rrr,
> +    .out_rri = tgen_addcio_rri,
>   };
>   
>   static const TCGOutOpAddSubCarry outop_addci = {
> -    .base.static_constraint = C_NotImplemented,
> -};
> -
> -static const TCGOutOpBinary outop_addcio = {
> -    .base.static_constraint = C_NotImplemented,
> +    .base.static_constraint = C_Dynamic,
> +    .base.dynamic_constraint = cset_addcio,
> +    .out_rrr = tgen_addcio_rrr,
> +    .out_rri = tgen_addcio_rri,
>   };
>   
>   static void tcg_out_set_carry(TCGContext *s)
>   {
> -    g_assert_not_reached();
> +    tcg_out32(s, SUBFC | TAB(TCG_REG_R0, TCG_REG_R0, TCG_REG_R0));
>   }
>   
>   static void tgen_and(TCGContext *s, TCGType type,
> @@ -3284,21 +3336,94 @@ static const TCGOutOpSubtract outop_sub = {
>       .out_rir = tgen_subfi,
>   };
>   
> +static void tgen_subbo_rrr(TCGContext *s, TCGType type,
> +                           TCGReg a0, TCGReg a1, TCGReg a2)
> +{
> +    tcg_out32(s, SUBFC | TAB(a0, a2, a1));
> +}
> +
> +static void tgen_subbo_rri(TCGContext *s, TCGType type,
> +                           TCGReg a0, TCGReg a1, tcg_target_long a2)
> +{
> +    if (a2 == 0) {
> +        tcg_out_movi(s, type, TCG_REG_R0, 0);
> +        tgen_subbo_rrr(s, type, a0, a1, TCG_REG_R0);
> +    } else {
> +        tgen_addco_rri(s, type, a0, a1, -a2);
> +    }
> +}
> +
> +/* The underlying insn for subfi is subfic. */
> +#define tgen_subbo_rir  tgen_subfi
> +
> +static void tgen_subbo_rii(TCGContext *s, TCGType type,
> +                           TCGReg a0, tcg_target_long a1, tcg_target_long a2)
> +{
> +    tcg_out_movi(s, type, TCG_REG_R0, a2);
> +    tgen_subbo_rir(s, type, a0, a1, TCG_REG_R0);
> +}
> +
> +static TCGConstraintSetIndex cset_subbo(TCGType type, unsigned flags)
> +{
> +    /* Recall that the CA bit is defined based on the host word size. */
> +    return type == TCG_TYPE_REG ? C_O1_I2(r, rI, rN) : C_NotImplemented;
> +}
> +
>   static const TCGOutOpAddSubCarry outop_subbo = {
> -    .base.static_constraint = C_NotImplemented,
> +    .base.static_constraint = C_Dynamic,
> +    .base.dynamic_constraint = cset_subbo,
> +    .out_rrr = tgen_subbo_rrr,
> +    .out_rri = tgen_subbo_rri,
> +    .out_rir = tgen_subbo_rir,
> +    .out_rii = tgen_subbo_rii,
>   };
>   
> -static const TCGOutOpAddSubCarry outop_subbi = {
> -    .base.static_constraint = C_NotImplemented,
> -};
> +static void tgen_subbio_rrr(TCGContext *s, TCGType type,
> +                            TCGReg a0, TCGReg a1, TCGReg a2)
> +{
> +    tcg_out32(s, SUBFE | TAB(a0, a2, a1));
> +}
> +
> +static void tgen_subbio_rri(TCGContext *s, TCGType type,
> +                            TCGReg a0, TCGReg a1, tcg_target_long a2)
> +{
> +    tgen_addcio_rri(s, type, a0, a1, ~a2);
> +}
> +
> +static void tgen_subbio_rir(TCGContext *s, TCGType type,
> +                            TCGReg a0, tcg_target_long a1, TCGReg a2)
> +{
> +    tcg_debug_assert(a1 == 0 || a1 == -1);
> +    tcg_out32(s, (a1 ? SUBFME : SUBFZE) | RT(a0) | RA(a2));
> +}
> +
> +static void tgen_subbio_rii(TCGContext *s, TCGType type,
> +                            TCGReg a0, tcg_target_long a1, tcg_target_long a2)
> +{
> +    tcg_out_movi(s, type, TCG_REG_R0, a2);
> +    tgen_subbio_rir(s, type, a0, a1, TCG_REG_R0);
> +}
> +
> +static TCGConstraintSetIndex cset_subbio(TCGType type, unsigned flags)
> +{
> +    return type == TCG_TYPE_REG ? C_O1_I2(r, rZM, rZM) : C_NotImplemented;
> +}
>   
>   static const TCGOutOpAddSubCarry outop_subbio = {
> -    .base.static_constraint = C_NotImplemented,
> +    .base.static_constraint = C_Dynamic,
> +    .base.dynamic_constraint = cset_subbio,
> +    .out_rrr = tgen_subbio_rrr,
> +    .out_rri = tgen_subbio_rri,
> +    .out_rir = tgen_subbio_rir,
> +    .out_rii = tgen_subbio_rii,
>   };
>   
> +#define outop_subbi  outop_subbio
> +
>   static void tcg_out_set_borrow(TCGContext *s)
>   {
> -    g_assert_not_reached();
> +    /* borrow = !carry */
> +    tcg_out32(s, ADDIC | TAI(TCG_REG_R0, TCG_REG_R0, 0));
>   }
>   
>   static void tgen_xor(TCGContext *s, TCGType type,

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
diff mbox series

Patch

diff --git a/tcg/ppc/tcg-target-con-set.h b/tcg/ppc/tcg-target-con-set.h
index 14cd217287..9ea26c40ae 100644
--- a/tcg/ppc/tcg-target-con-set.h
+++ b/tcg/ppc/tcg-target-con-set.h
@@ -29,7 +29,10 @@  C_O1_I2(r, r, rC)
 C_O1_I2(r, r, rI)
 C_O1_I2(r, r, rT)
 C_O1_I2(r, r, rU)
+C_O1_I2(r, r, rZM)
 C_O1_I2(r, r, rZW)
+C_O1_I2(r, rI, rN)
+C_O1_I2(r, rZM, rZM)
 C_O1_I2(v, v, v)
 C_O1_I3(v, v, v, v)
 C_O1_I4(v, v, v, vZM, v)
diff --git a/tcg/ppc/tcg-target-con-str.h b/tcg/ppc/tcg-target-con-str.h
index 16b687216e..faf92da47f 100644
--- a/tcg/ppc/tcg-target-con-str.h
+++ b/tcg/ppc/tcg-target-con-str.h
@@ -19,6 +19,7 @@  REGS('v', ALL_VECTOR_REGS)
 CONST('C', TCG_CT_CONST_CMP)
 CONST('I', TCG_CT_CONST_S16)
 CONST('M', TCG_CT_CONST_MONE)
+CONST('N', TCG_CT_CONST_N16)
 CONST('T', TCG_CT_CONST_S32)
 CONST('U', TCG_CT_CONST_U32)
 CONST('W', TCG_CT_CONST_WSZ)
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index 5b04655f3b..0b151db0e4 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -89,14 +89,15 @@ 
 /* Shorthand for size of a register.  */
 #define SZR  (TCG_TARGET_REG_BITS / 8)
 
-#define TCG_CT_CONST_S16  0x100
-#define TCG_CT_CONST_U16  0x200
-#define TCG_CT_CONST_S32  0x400
-#define TCG_CT_CONST_U32  0x800
-#define TCG_CT_CONST_ZERO 0x1000
-#define TCG_CT_CONST_MONE 0x2000
-#define TCG_CT_CONST_WSZ  0x4000
-#define TCG_CT_CONST_CMP  0x8000
+#define TCG_CT_CONST_S16     0x00100
+#define TCG_CT_CONST_U16     0x00200
+#define TCG_CT_CONST_N16     0x00400
+#define TCG_CT_CONST_S32     0x00800
+#define TCG_CT_CONST_U32     0x01000
+#define TCG_CT_CONST_ZERO    0x02000
+#define TCG_CT_CONST_MONE    0x04000
+#define TCG_CT_CONST_WSZ     0x08000
+#define TCG_CT_CONST_CMP     0x10000
 
 #define ALL_GENERAL_REGS  0xffffffffu
 #define ALL_VECTOR_REGS   0xffffffff00000000ull
@@ -342,6 +343,9 @@  static bool tcg_target_const_match(int64_t sval, int ct,
     if ((ct & TCG_CT_CONST_U16) && uval == (uint16_t)uval) {
         return 1;
     }
+    if ((ct & TCG_CT_CONST_N16) && -sval == (int16_t)-sval) {
+        return 1;
+    }
     if ((ct & TCG_CT_CONST_S32) && sval == (int32_t)sval) {
         return 1;
     }
@@ -2863,21 +2867,69 @@  static const TCGOutOpBinary outop_add = {
     .out_rri = tgen_addi,
 };
 
+static void tgen_addco_rrr(TCGContext *s, TCGType type,
+                           TCGReg a0, TCGReg a1, TCGReg a2)
+{
+    tcg_out32(s, ADDC | TAB(a0, a1, a2));
+}
+
+static void tgen_addco_rri(TCGContext *s, TCGType type,
+                           TCGReg a0, TCGReg a1, tcg_target_long a2)
+{
+    tcg_out32(s, ADDIC | TAI(a0, a1, a2));
+}
+
+static TCGConstraintSetIndex cset_addco(TCGType type, unsigned flags)
+{
+    /*
+     * Note that the CA bit is defined based on the word size of the
+     * environment.  So in 64-bit mode it's always carry-out of bit 63.
+     * The fallback code using deposit works just as well for TCG_TYPE_I32.
+     */
+    return type == TCG_TYPE_REG ? C_O1_I2(r, r, rI) : C_NotImplemented;
+}
+
 static const TCGOutOpBinary outop_addco = {
-    .base.static_constraint = C_NotImplemented,
+    .base.static_constraint = C_Dynamic,
+    .base.dynamic_constraint = cset_addco,
+    .out_rrr = tgen_addco_rrr,
+    .out_rri = tgen_addco_rri,
+};
+
+static void tgen_addcio_rrr(TCGContext *s, TCGType type,
+                            TCGReg a0, TCGReg a1, TCGReg a2)
+{
+    tcg_out32(s, ADDE | TAB(a0, a1, a2));
+}
+
+static void tgen_addcio_rri(TCGContext *s, TCGType type,
+                            TCGReg a0, TCGReg a1, tcg_target_long a2)
+{
+    tcg_out32(s, (a2 ? ADDME : ADDZE) | RT(a0) | RA(a1));
+}
+
+static TCGConstraintSetIndex cset_addcio(TCGType type, unsigned flags)
+{
+    return type == TCG_TYPE_REG ? C_O1_I2(r, r, rZM) : C_NotImplemented;
+}
+
+static const TCGOutOpBinary outop_addcio = {
+    .base.static_constraint = C_Dynamic,
+    .base.dynamic_constraint = cset_addcio,
+    .out_rrr = tgen_addcio_rrr,
+    .out_rri = tgen_addcio_rri,
 };
 
 static const TCGOutOpAddSubCarry outop_addci = {
-    .base.static_constraint = C_NotImplemented,
-};
-
-static const TCGOutOpBinary outop_addcio = {
-    .base.static_constraint = C_NotImplemented,
+    .base.static_constraint = C_Dynamic,
+    .base.dynamic_constraint = cset_addcio,
+    .out_rrr = tgen_addcio_rrr,
+    .out_rri = tgen_addcio_rri,
 };
 
 static void tcg_out_set_carry(TCGContext *s)
 {
-    g_assert_not_reached();
+    tcg_out32(s, SUBFC | TAB(TCG_REG_R0, TCG_REG_R0, TCG_REG_R0));
 }
 
 static void tgen_and(TCGContext *s, TCGType type,
@@ -3284,21 +3336,94 @@  static const TCGOutOpSubtract outop_sub = {
     .out_rir = tgen_subfi,
 };
 
+static void tgen_subbo_rrr(TCGContext *s, TCGType type,
+                           TCGReg a0, TCGReg a1, TCGReg a2)
+{
+    tcg_out32(s, SUBFC | TAB(a0, a2, a1));
+}
+
+static void tgen_subbo_rri(TCGContext *s, TCGType type,
+                           TCGReg a0, TCGReg a1, tcg_target_long a2)
+{
+    if (a2 == 0) {
+        tcg_out_movi(s, type, TCG_REG_R0, 0);
+        tgen_subbo_rrr(s, type, a0, a1, TCG_REG_R0);
+    } else {
+        tgen_addco_rri(s, type, a0, a1, -a2);
+    }
+}
+
+/* The underlying insn for subfi is subfic. */
+#define tgen_subbo_rir  tgen_subfi
+
+static void tgen_subbo_rii(TCGContext *s, TCGType type,
+                           TCGReg a0, tcg_target_long a1, tcg_target_long a2)
+{
+    tcg_out_movi(s, type, TCG_REG_R0, a2);
+    tgen_subbo_rir(s, type, a0, a1, TCG_REG_R0);
+}
+
+static TCGConstraintSetIndex cset_subbo(TCGType type, unsigned flags)
+{
+    /* Recall that the CA bit is defined based on the host word size. */
+    return type == TCG_TYPE_REG ? C_O1_I2(r, rI, rN) : C_NotImplemented;
+}
+
 static const TCGOutOpAddSubCarry outop_subbo = {
-    .base.static_constraint = C_NotImplemented,
+    .base.static_constraint = C_Dynamic,
+    .base.dynamic_constraint = cset_subbo,
+    .out_rrr = tgen_subbo_rrr,
+    .out_rri = tgen_subbo_rri,
+    .out_rir = tgen_subbo_rir,
+    .out_rii = tgen_subbo_rii,
 };
 
-static const TCGOutOpAddSubCarry outop_subbi = {
-    .base.static_constraint = C_NotImplemented,
-};
+static void tgen_subbio_rrr(TCGContext *s, TCGType type,
+                            TCGReg a0, TCGReg a1, TCGReg a2)
+{
+    tcg_out32(s, SUBFE | TAB(a0, a2, a1));
+}
+
+static void tgen_subbio_rri(TCGContext *s, TCGType type,
+                            TCGReg a0, TCGReg a1, tcg_target_long a2)
+{
+    tgen_addcio_rri(s, type, a0, a1, ~a2);
+}
+
+static void tgen_subbio_rir(TCGContext *s, TCGType type,
+                            TCGReg a0, tcg_target_long a1, TCGReg a2)
+{
+    tcg_debug_assert(a1 == 0 || a1 == -1);
+    tcg_out32(s, (a1 ? SUBFME : SUBFZE) | RT(a0) | RA(a2));
+}
+
+static void tgen_subbio_rii(TCGContext *s, TCGType type,
+                            TCGReg a0, tcg_target_long a1, tcg_target_long a2)
+{
+    tcg_out_movi(s, type, TCG_REG_R0, a2);
+    tgen_subbio_rir(s, type, a0, a1, TCG_REG_R0);
+}
+
+static TCGConstraintSetIndex cset_subbio(TCGType type, unsigned flags)
+{
+    return type == TCG_TYPE_REG ? C_O1_I2(r, rZM, rZM) : C_NotImplemented;
+}
 
 static const TCGOutOpAddSubCarry outop_subbio = {
-    .base.static_constraint = C_NotImplemented,
+    .base.static_constraint = C_Dynamic,
+    .base.dynamic_constraint = cset_subbio,
+    .out_rrr = tgen_subbio_rrr,
+    .out_rri = tgen_subbio_rri,
+    .out_rir = tgen_subbio_rir,
+    .out_rii = tgen_subbio_rii,
 };
 
+#define outop_subbi  outop_subbio
+
 static void tcg_out_set_borrow(TCGContext *s)
 {
-    g_assert_not_reached();
+    /* borrow = !carry */
+    tcg_out32(s, ADDIC | TAI(TCG_REG_R0, TCG_REG_R0, 0));
 }
 
 static void tgen_xor(TCGContext *s, TCGType type,