| Message ID | 20250415192515.232910-140-richard.henderson@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | tcg: Convert to TCGOutOp structures | expand |
On 4/15/25 12:24, Richard Henderson wrote: > Do not clobber flags if they're live. Required in order > to perform register allocation on add/sub carry opcodes. > LA and AGHI are the same size, so use LA unconditionally. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > tcg/s390x/tcg-target.c.inc | 35 +++++++++++++++++++++-------------- > 1 file changed, 21 insertions(+), 14 deletions(-) > > diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc > index a30afb455e..e262876614 100644 > --- a/tcg/s390x/tcg-target.c.inc > +++ b/tcg/s390x/tcg-target.c.inc > @@ -951,25 +951,32 @@ static void tcg_out_movi(TCGContext *s, TCGType type, > if (pc_off == (int32_t)pc_off) { > tcg_out_insn(s, RIL, LARL, ret, pc_off); > if (sval & 1) { > - tcg_out_insn(s, RI, AGHI, ret, 1); > + tcg_out_insn(s, RX, LA, ret, ret, TCG_REG_NONE, 1); > } > return; > } > > - /* Otherwise, load it by parts. */ > - i = is_const_p16((uint32_t)uval); > - if (i >= 0) { > - tcg_out_insn_RI(s, li_insns[i], ret, uval >> (i * 16)); > - } else { > - tcg_out_insn(s, RIL, LLILF, ret, uval); > - } > - uval >>= 32; > - i = is_const_p16(uval); > - if (i >= 0) { > - tcg_out_insn_RI(s, oi_insns[i + 2], ret, uval >> (i * 16)); > - } else { > - tcg_out_insn(s, RIL, OIHF, ret, uval); > + if (!s->carry_live) { > + /* Load by parts, at most 2 instructions. */ > + i = is_const_p16((uint32_t)uval); > + if (i >= 0) { > + tcg_out_insn_RI(s, li_insns[i], ret, uval >> (i * 16)); > + } else { > + tcg_out_insn(s, RIL, LLILF, ret, uval); > + } > + uval >>= 32; > + i = is_const_p16(uval); > + if (i >= 0) { > + tcg_out_insn_RI(s, oi_insns[i + 2], ret, uval >> (i * 16)); > + } else { > + tcg_out_insn(s, RIL, OIHF, ret, uval); > + } > + return; > } > + > + /* Otherwise, stuff it in the constant pool. */ > + tcg_out_insn(s, RIL, LGRL, ret, 0); > + new_pool_label(s, sval, R_390_PC32DBL, s->code_ptr - 2, 2); > } > > /* Emit a load/store type instruction. Inputs are: Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index a30afb455e..e262876614 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -951,25 +951,32 @@ static void tcg_out_movi(TCGContext *s, TCGType type, if (pc_off == (int32_t)pc_off) { tcg_out_insn(s, RIL, LARL, ret, pc_off); if (sval & 1) { - tcg_out_insn(s, RI, AGHI, ret, 1); + tcg_out_insn(s, RX, LA, ret, ret, TCG_REG_NONE, 1); } return; } - /* Otherwise, load it by parts. */ - i = is_const_p16((uint32_t)uval); - if (i >= 0) { - tcg_out_insn_RI(s, li_insns[i], ret, uval >> (i * 16)); - } else { - tcg_out_insn(s, RIL, LLILF, ret, uval); - } - uval >>= 32; - i = is_const_p16(uval); - if (i >= 0) { - tcg_out_insn_RI(s, oi_insns[i + 2], ret, uval >> (i * 16)); - } else { - tcg_out_insn(s, RIL, OIHF, ret, uval); + if (!s->carry_live) { + /* Load by parts, at most 2 instructions. */ + i = is_const_p16((uint32_t)uval); + if (i >= 0) { + tcg_out_insn_RI(s, li_insns[i], ret, uval >> (i * 16)); + } else { + tcg_out_insn(s, RIL, LLILF, ret, uval); + } + uval >>= 32; + i = is_const_p16(uval); + if (i >= 0) { + tcg_out_insn_RI(s, oi_insns[i + 2], ret, uval >> (i * 16)); + } else { + tcg_out_insn(s, RIL, OIHF, ret, uval); + } + return; } + + /* Otherwise, stuff it in the constant pool. */ + tcg_out_insn(s, RIL, LGRL, ret, 0); + new_pool_label(s, sval, R_390_PC32DBL, s->code_ptr - 2, 2); } /* Emit a load/store type instruction. Inputs are:
Do not clobber flags if they're live. Required in order to perform register allocation on add/sub carry opcodes. LA and AGHI are the same size, so use LA unconditionally. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- tcg/s390x/tcg-target.c.inc | 35 +++++++++++++++++++++-------------- 1 file changed, 21 insertions(+), 14 deletions(-)