| Message ID | 20250415192515.232910-151-richard.henderson@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | tcg: Convert to TCGOutOp structures | expand |
On 4/15/25 12:25, Richard Henderson wrote: > Most tcg backends already have a function for this; > the rest can split one out from tcg_out_op. > Call it directly from tcg_gen_code. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > tcg/tcg.c | 4 ++++ > tcg/aarch64/tcg-target.c.inc | 6 +----- > tcg/arm/tcg-target.c.inc | 6 +----- > tcg/i386/tcg-target.c.inc | 5 +---- > tcg/loongarch64/tcg-target.c.inc | 6 +----- > tcg/mips/tcg-target.c.inc | 5 +---- > tcg/ppc/tcg-target.c.inc | 6 +----- > tcg/riscv/tcg-target.c.inc | 6 +----- > tcg/s390x/tcg-target.c.inc | 20 +++++++++++--------- > tcg/sparc64/tcg-target.c.inc | 6 +----- > tcg/tci/tcg-target.c.inc | 9 +++++---- > 11 files changed, 28 insertions(+), 51 deletions(-) > > diff --git a/tcg/tcg.c b/tcg/tcg.c > index ffabe43c91..4ffd4d203b 100644 > --- a/tcg/tcg.c > +++ b/tcg/tcg.c > @@ -133,6 +133,7 @@ static void tcg_out_addi_ptr(TCGContext *s, TCGReg, TCGReg, tcg_target_long); > static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2); > static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg); > static void tcg_out_goto_tb(TCGContext *s, int which); > +static void tcg_out_mb(TCGContext *s, unsigned bar); > static void tcg_out_set_carry(TCGContext *s); > static void tcg_out_set_borrow(TCGContext *s); > static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, > @@ -6894,6 +6895,9 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb, uint64_t pc_start) > case INDEX_op_goto_tb: > tcg_out_goto_tb(s, op->args[0]); > break; > + case INDEX_op_mb: > + tcg_out_mb(s, op->args[0]); > + break; > case INDEX_op_dup2_vec: > if (tcg_reg_alloc_dup2(s, op)) { > break; > diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc > index 75cf490fd2..d2babd9bab 100644 > --- a/tcg/aarch64/tcg-target.c.inc > +++ b/tcg/aarch64/tcg-target.c.inc > @@ -1575,7 +1575,7 @@ static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rn) > tcg_out_mov(s, TCG_TYPE_I32, rd, rn); > } > > -static inline void tcg_out_mb(TCGContext *s, TCGArg a0) > +static void tcg_out_mb(TCGContext *s, unsigned a0) > { > static const uint32_t sync[] = { > [0 ... TCG_MO_ALL] = DMB_ISH | DMB_LD | DMB_ST, > @@ -2845,10 +2845,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType ext, > tcg_out_qemu_ldst_i128(s, a0, a1, a2, args[3], false); > break; > > - case INDEX_op_mb: > - tcg_out_mb(s, a0); > - break; > - > case INDEX_op_call: /* Always emitted via tcg_out_call. */ > case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ > case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ > diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc > index 3c9042ebfa..131901dabc 100644 > --- a/tcg/arm/tcg-target.c.inc > +++ b/tcg/arm/tcg-target.c.inc > @@ -1203,7 +1203,7 @@ static void tcg_out_goto_label(TCGContext *s, ARMCond cond, TCGLabel *l) > } > } > > -static void tcg_out_mb(TCGContext *s, TCGArg a0) > +static void tcg_out_mb(TCGContext *s, unsigned a0) > { > if (use_armv7_instructions) { > tcg_out32(s, INSN_DMB_ISH); > @@ -2565,10 +2565,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, > tcg_out_qemu_st(s, args[0], args[1], args[2], args[3], TCG_TYPE_I64); > break; > > - case INDEX_op_mb: > - tcg_out_mb(s, args[0]); > - break; > - > case INDEX_op_call: /* Always emitted via tcg_out_call. */ > case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ > case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ > diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc > index da05f13b21..bf84f9f455 100644 > --- a/tcg/i386/tcg-target.c.inc > +++ b/tcg/i386/tcg-target.c.inc > @@ -1168,7 +1168,7 @@ static inline void tcg_out_pushi(TCGContext *s, tcg_target_long val) > } > } > > -static inline void tcg_out_mb(TCGContext *s, TCGArg a0) > +static void tcg_out_mb(TCGContext *s, unsigned a0) > { > /* Given the strength of x86 memory ordering, we only need care for > store-load ordering. Experimentally, "lock orl $0,0(%esp)" is > @@ -3536,9 +3536,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, > break; > #endif > > - case INDEX_op_mb: > - tcg_out_mb(s, a0); > - break; > case INDEX_op_call: /* Always emitted via tcg_out_call. */ > case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ > case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ > diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc > index 937f19fe6b..b9b05b8c25 100644 > --- a/tcg/loongarch64/tcg-target.c.inc > +++ b/tcg/loongarch64/tcg-target.c.inc > @@ -289,7 +289,7 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type, > * TCG intrinsics > */ > > -static void tcg_out_mb(TCGContext *s, TCGArg a0) > +static void tcg_out_mb(TCGContext *s, unsigned a0) > { > /* Baseline LoongArch only has the full barrier, unfortunately. */ > tcg_out_opc_dbar(s, 0); > @@ -1905,10 +1905,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, > TCGArg a3 = args[3]; > > switch (opc) { > - case INDEX_op_mb: > - tcg_out_mb(s, a0); > - break; > - > case INDEX_op_goto_ptr: > tcg_out_opc_jirl(s, TCG_REG_ZERO, a0, 0); > break; > diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc > index 0c268cef42..b0da661561 100644 > --- a/tcg/mips/tcg-target.c.inc > +++ b/tcg/mips/tcg-target.c.inc > @@ -1491,7 +1491,7 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi, > } > } > > -static void tcg_out_mb(TCGContext *s, TCGArg a0) > +static void tcg_out_mb(TCGContext *s, unsigned a0) > { > static const MIPSInsn sync[] = { > /* Note that SYNC_MB is a slightly weaker than SYNC 0, > @@ -2352,9 +2352,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, > } > break; > > - case INDEX_op_mb: > - tcg_out_mb(s, a0); > - break; > case INDEX_op_call: /* Always emitted via tcg_out_call. */ > case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ > case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ > diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc > index 91df9610ec..ae18c84ae6 100644 > --- a/tcg/ppc/tcg-target.c.inc > +++ b/tcg/ppc/tcg-target.c.inc > @@ -2208,7 +2208,7 @@ static const TCGOutOpBrcond2 outop_brcond2 = { > .out = tgen_brcond2, > }; > > -static void tcg_out_mb(TCGContext *s, TCGArg a0) > +static void tcg_out_mb(TCGContext *s, unsigned a0) > { > uint32_t insn; > > @@ -3758,10 +3758,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, > tcg_out_qemu_ldst_i128(s, args[0], args[1], args[2], args[3], false); > break; > > - case INDEX_op_mb: > - tcg_out_mb(s, args[0]); > - break; > - > case INDEX_op_call: /* Always emitted via tcg_out_call. */ > case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ > case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ > diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc > index 707ebb8f6d..df271752b7 100644 > --- a/tcg/riscv/tcg-target.c.inc > +++ b/tcg/riscv/tcg-target.c.inc > @@ -1582,7 +1582,7 @@ static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg, > tcg_out_call_int(s, arg, false); > } > > -static void tcg_out_mb(TCGContext *s, TCGArg a0) > +static void tcg_out_mb(TCGContext *s, unsigned a0) > { > tcg_insn_unit insn = OPC_FENCE; > > @@ -2594,10 +2594,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, > tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I64); > break; > > - case INDEX_op_mb: > - tcg_out_mb(s, a0); > - break; > - > case INDEX_op_call: /* Always emitted via tcg_out_call. */ > case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ > case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ > diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc > index 09c7ca5b44..020d8ba73f 100644 > --- a/tcg/s390x/tcg-target.c.inc > +++ b/tcg/s390x/tcg-target.c.inc > @@ -3008,6 +3008,17 @@ static const TCGOutOpUnary outop_not = { > .out_rr = tgen_not, > }; > > +static void tcg_out_mb(TCGContext *s, unsigned a0) > +{ > + /* > + * The host memory model is quite strong, we simply need to > + * serialize the instruction stream. > + */ > + if (a0 & TCG_MO_ST_LD) { > + /* fast-bcr-serialization facility (45) is present */ > + tcg_out_insn(s, RR, BCR, 14, 0); > + } > +} > > # define OP_32_64(x) \ > case glue(glue(INDEX_op_,x),_i32): \ > @@ -3107,15 +3118,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, > tcg_out_st(s, TCG_TYPE_I64, args[0], args[1], args[2]); > break; > > - case INDEX_op_mb: > - /* The host memory model is quite strong, we simply need to > - serialize the instruction stream. */ > - if (args[0] & TCG_MO_ST_LD) { > - /* fast-bcr-serialization facility (45) is present */ > - tcg_out_insn(s, RR, BCR, 14, 0); > - } > - break; > - > case INDEX_op_call: /* Always emitted via tcg_out_call. */ > case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ > case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ > diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc > index 842ef68c54..56b68fe841 100644 > --- a/tcg/sparc64/tcg-target.c.inc > +++ b/tcg/sparc64/tcg-target.c.inc > @@ -949,7 +949,7 @@ static void tcg_out_call(TCGContext *s, const tcg_insn_unit *dest, > tcg_out_nop(s); > } > > -static void tcg_out_mb(TCGContext *s, TCGArg a0) > +static void tcg_out_mb(TCGContext *s, unsigned a0) > { > /* Note that the TCG memory order constants mirror the Sparc MEMBAR. */ > tcg_out32(s, MEMBAR | (a0 & TCG_MO_ALL)); > @@ -2020,10 +2020,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, > tcg_out_ldst(s, a0, a1, a2, STX); > break; > > - case INDEX_op_mb: > - tcg_out_mb(s, a0); > - break; > - > case INDEX_op_call: /* Always emitted via tcg_out_call. */ > case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ > case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ > diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc > index 35c0c91f3e..64d4ac07cd 100644 > --- a/tcg/tci/tcg-target.c.inc > +++ b/tcg/tci/tcg-target.c.inc > @@ -1131,6 +1131,11 @@ static const TCGOutOpSetcond2 outop_setcond2 = { > .out = tgen_setcond2, > }; > > +static void tcg_out_mb(TCGContext *s, unsigned a0) > +{ > + tcg_out_op_v(s, INDEX_op_mb); > +} > + > static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, > const TCGArg args[TCG_MAX_OP_ARGS], > const int const_args[TCG_MAX_OP_ARGS]) > @@ -1178,10 +1183,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, > } > break; > > - case INDEX_op_mb: > - tcg_out_op_v(s, opc); > - break; > - > case INDEX_op_call: /* Always emitted via tcg_out_call. */ > case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ > case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
diff --git a/tcg/tcg.c b/tcg/tcg.c index ffabe43c91..4ffd4d203b 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -133,6 +133,7 @@ static void tcg_out_addi_ptr(TCGContext *s, TCGReg, TCGReg, tcg_target_long); static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2); static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg); static void tcg_out_goto_tb(TCGContext *s, int which); +static void tcg_out_mb(TCGContext *s, unsigned bar); static void tcg_out_set_carry(TCGContext *s); static void tcg_out_set_borrow(TCGContext *s); static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, @@ -6894,6 +6895,9 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb, uint64_t pc_start) case INDEX_op_goto_tb: tcg_out_goto_tb(s, op->args[0]); break; + case INDEX_op_mb: + tcg_out_mb(s, op->args[0]); + break; case INDEX_op_dup2_vec: if (tcg_reg_alloc_dup2(s, op)) { break; diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 75cf490fd2..d2babd9bab 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1575,7 +1575,7 @@ static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rn) tcg_out_mov(s, TCG_TYPE_I32, rd, rn); } -static inline void tcg_out_mb(TCGContext *s, TCGArg a0) +static void tcg_out_mb(TCGContext *s, unsigned a0) { static const uint32_t sync[] = { [0 ... TCG_MO_ALL] = DMB_ISH | DMB_LD | DMB_ST, @@ -2845,10 +2845,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType ext, tcg_out_qemu_ldst_i128(s, a0, a1, a2, args[3], false); break; - case INDEX_op_mb: - tcg_out_mb(s, a0); - break; - case INDEX_op_call: /* Always emitted via tcg_out_call. */ case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 3c9042ebfa..131901dabc 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -1203,7 +1203,7 @@ static void tcg_out_goto_label(TCGContext *s, ARMCond cond, TCGLabel *l) } } -static void tcg_out_mb(TCGContext *s, TCGArg a0) +static void tcg_out_mb(TCGContext *s, unsigned a0) { if (use_armv7_instructions) { tcg_out32(s, INSN_DMB_ISH); @@ -2565,10 +2565,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, tcg_out_qemu_st(s, args[0], args[1], args[2], args[3], TCG_TYPE_I64); break; - case INDEX_op_mb: - tcg_out_mb(s, args[0]); - break; - case INDEX_op_call: /* Always emitted via tcg_out_call. */ case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index da05f13b21..bf84f9f455 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1168,7 +1168,7 @@ static inline void tcg_out_pushi(TCGContext *s, tcg_target_long val) } } -static inline void tcg_out_mb(TCGContext *s, TCGArg a0) +static void tcg_out_mb(TCGContext *s, unsigned a0) { /* Given the strength of x86 memory ordering, we only need care for store-load ordering. Experimentally, "lock orl $0,0(%esp)" is @@ -3536,9 +3536,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, break; #endif - case INDEX_op_mb: - tcg_out_mb(s, a0); - break; case INDEX_op_call: /* Always emitted via tcg_out_call. */ case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc index 937f19fe6b..b9b05b8c25 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -289,7 +289,7 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type, * TCG intrinsics */ -static void tcg_out_mb(TCGContext *s, TCGArg a0) +static void tcg_out_mb(TCGContext *s, unsigned a0) { /* Baseline LoongArch only has the full barrier, unfortunately. */ tcg_out_opc_dbar(s, 0); @@ -1905,10 +1905,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, TCGArg a3 = args[3]; switch (opc) { - case INDEX_op_mb: - tcg_out_mb(s, a0); - break; - case INDEX_op_goto_ptr: tcg_out_opc_jirl(s, TCG_REG_ZERO, a0, 0); break; diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 0c268cef42..b0da661561 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -1491,7 +1491,7 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi, } } -static void tcg_out_mb(TCGContext *s, TCGArg a0) +static void tcg_out_mb(TCGContext *s, unsigned a0) { static const MIPSInsn sync[] = { /* Note that SYNC_MB is a slightly weaker than SYNC 0, @@ -2352,9 +2352,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, } break; - case INDEX_op_mb: - tcg_out_mb(s, a0); - break; case INDEX_op_call: /* Always emitted via tcg_out_call. */ case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 91df9610ec..ae18c84ae6 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -2208,7 +2208,7 @@ static const TCGOutOpBrcond2 outop_brcond2 = { .out = tgen_brcond2, }; -static void tcg_out_mb(TCGContext *s, TCGArg a0) +static void tcg_out_mb(TCGContext *s, unsigned a0) { uint32_t insn; @@ -3758,10 +3758,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, tcg_out_qemu_ldst_i128(s, args[0], args[1], args[2], args[3], false); break; - case INDEX_op_mb: - tcg_out_mb(s, args[0]); - break; - case INDEX_op_call: /* Always emitted via tcg_out_call. */ case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 707ebb8f6d..df271752b7 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -1582,7 +1582,7 @@ static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg, tcg_out_call_int(s, arg, false); } -static void tcg_out_mb(TCGContext *s, TCGArg a0) +static void tcg_out_mb(TCGContext *s, unsigned a0) { tcg_insn_unit insn = OPC_FENCE; @@ -2594,10 +2594,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I64); break; - case INDEX_op_mb: - tcg_out_mb(s, a0); - break; - case INDEX_op_call: /* Always emitted via tcg_out_call. */ case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 09c7ca5b44..020d8ba73f 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -3008,6 +3008,17 @@ static const TCGOutOpUnary outop_not = { .out_rr = tgen_not, }; +static void tcg_out_mb(TCGContext *s, unsigned a0) +{ + /* + * The host memory model is quite strong, we simply need to + * serialize the instruction stream. + */ + if (a0 & TCG_MO_ST_LD) { + /* fast-bcr-serialization facility (45) is present */ + tcg_out_insn(s, RR, BCR, 14, 0); + } +} # define OP_32_64(x) \ case glue(glue(INDEX_op_,x),_i32): \ @@ -3107,15 +3118,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, tcg_out_st(s, TCG_TYPE_I64, args[0], args[1], args[2]); break; - case INDEX_op_mb: - /* The host memory model is quite strong, we simply need to - serialize the instruction stream. */ - if (args[0] & TCG_MO_ST_LD) { - /* fast-bcr-serialization facility (45) is present */ - tcg_out_insn(s, RR, BCR, 14, 0); - } - break; - case INDEX_op_call: /* Always emitted via tcg_out_call. */ case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index 842ef68c54..56b68fe841 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -949,7 +949,7 @@ static void tcg_out_call(TCGContext *s, const tcg_insn_unit *dest, tcg_out_nop(s); } -static void tcg_out_mb(TCGContext *s, TCGArg a0) +static void tcg_out_mb(TCGContext *s, unsigned a0) { /* Note that the TCG memory order constants mirror the Sparc MEMBAR. */ tcg_out32(s, MEMBAR | (a0 & TCG_MO_ALL)); @@ -2020,10 +2020,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, tcg_out_ldst(s, a0, a1, a2, STX); break; - case INDEX_op_mb: - tcg_out_mb(s, a0); - break; - case INDEX_op_call: /* Always emitted via tcg_out_call. */ case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 35c0c91f3e..64d4ac07cd 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -1131,6 +1131,11 @@ static const TCGOutOpSetcond2 outop_setcond2 = { .out = tgen_setcond2, }; +static void tcg_out_mb(TCGContext *s, unsigned a0) +{ + tcg_out_op_v(s, INDEX_op_mb); +} + static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, const TCGArg args[TCG_MAX_OP_ARGS], const int const_args[TCG_MAX_OP_ARGS]) @@ -1178,10 +1183,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, } break; - case INDEX_op_mb: - tcg_out_op_v(s, opc); - break; - case INDEX_op_call: /* Always emitted via tcg_out_call. */ case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */
Most tcg backends already have a function for this; the rest can split one out from tcg_out_op. Call it directly from tcg_gen_code. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- tcg/tcg.c | 4 ++++ tcg/aarch64/tcg-target.c.inc | 6 +----- tcg/arm/tcg-target.c.inc | 6 +----- tcg/i386/tcg-target.c.inc | 5 +---- tcg/loongarch64/tcg-target.c.inc | 6 +----- tcg/mips/tcg-target.c.inc | 5 +---- tcg/ppc/tcg-target.c.inc | 6 +----- tcg/riscv/tcg-target.c.inc | 6 +----- tcg/s390x/tcg-target.c.inc | 20 +++++++++++--------- tcg/sparc64/tcg-target.c.inc | 6 +----- tcg/tci/tcg-target.c.inc | 9 +++++---- 11 files changed, 28 insertions(+), 51 deletions(-)