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[alternate,0/2] target/riscv: Fix write_misa vs aligned next_pc

Message ID 20250425165055.807801-1-richard.henderson@linaro.org
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Series target/riscv: Fix write_misa vs aligned next_pc | expand

Message

Richard Henderson April 25, 2025, 4:50 p.m. UTC 
This is an alternate, but less exact approach.  It assumes that there
will never be a 16 or 48-bit csr write instruction.  This feels dirtier,
but it's a fair assumption involves much less faff.


r~


Richard Henderson (2):
  target/riscv: Update pc before csrw, csrrw
  target/riscv: Fix write_misa vs aligned next_pc

 target/riscv/csr.c                      | 9 ++++++---
 target/riscv/insn_trans/trans_rvi.c.inc | 4 ++++
 2 files changed, 10 insertions(+), 3 deletions(-)

Comments

Philippe Mathieu-Daudé April 25, 2025, 10:35 p.m. UTC | #1 
On 25/4/25 18:50, Richard Henderson wrote:
> This is an alternate, but less exact approach.  It assumes that there
> will never be a 16 or 48-bit csr write instruction.  This feels dirtier,
> but it's a fair assumption involves much less faff.

I prefer the other safer version which properly propagate $ra, which
could be useful for callees.
Daniel Henrique Barboza April 26, 2025, 8:30 a.m. UTC | #2 
On 4/25/25 7:35 PM, Philippe Mathieu-Daudé wrote:
> On 25/4/25 18:50, Richard Henderson wrote:
>> This is an alternate, but less exact approach.  It assumes that there
>> will never be a 16 or 48-bit csr write instruction.  This feels dirtier,
>> but it's a fair assumption involves much less faff.
> 
> I prefer the other safer version which properly propagate $ra, which
> could be useful for callees.

Both are fine to me. Alistair can pick the one he likes more.



Thanks,

Daniel