| Message ID | 20250506080154.3995512-1-pritam.sutar@samsung.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v2] clk: samsung: correct clock summary for hsi1 block | expand |
Hi Pritam > -----Original Message----- > From: Pritam Manohar Sutar <pritam.sutar@samsung.com> > Sent: Tuesday, May 6, 2025 1:32 PM > To: krzk@kernel.org; s.nawrocki@samsung.com; cw00.choi@samsung.com; > alim.akhtar@samsung.com; mturquette@baylibre.com; sboyd@kernel.org; > sunyeal.hong@samsung.com > Cc: linux-samsung-soc@vger.kernel.org; linux-clk@vger.kernel.org; linux- > arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org; > rosa.pila@samsung.com; dev.tailor@samsung.com; > faraz.ata@samsung.com; Pritam Manohar Sutar > <pritam.sutar@samsung.com>; stable <stable@kernel.org> > Subject: [PATCH v2] clk: samsung: correct clock summary for hsi1 block > > clk_summary shows wrong value for "mout_hsi1_usbdrd_user". > It shows 400Mhz instead of 40Mhz as below. > > dout_shared2_div4 1 1 0 400000000 0 0 50000 Y ... > mout_hsi1_usbdrd_user 0 0 0 400000000 0 0 50000 Y ... > dout_clkcmu_hsi1_usbdrd 0 0 0 40000000 0 0 50000 Y ... > > Correct the clk_tree by adding correct clock parent for > "mout_hsi1_usbdrd_user". > > Post this change, clk_summary shows correct value. > > dout_shared2_div4 1 1 0 400000000 0 0 50000 Y ... > mout_clkcmu_hsi1_usbdrd 0 0 0 400000000 0 0 50000 Y ... > dout_clkcmu_hsi1_usbdrd 0 0 0 40000000 0 0 50000 Y ... > mout_hsi1_usbdrd_user 0 0 0 40000000 0 0 50000 Y ... > > Fixes: 485e13fe2fb6 ("clk: samsung: add top clock support for ExynosAuto > v920 SoC") > Cc: stable <stable@kernel.org> > Signed-off-by: Pritam Manohar Sutar <pritam.sutar@samsung.com> > --- Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
On 06/05/2025 10:01, Pritam Manohar Sutar wrote: > clk_summary shows wrong value for "mout_hsi1_usbdrd_user". > It shows 400Mhz instead of 40Mhz as below. > > dout_shared2_div4 1 1 0 400000000 0 0 50000 Y ... > mout_hsi1_usbdrd_user 0 0 0 400000000 0 0 50000 Y ... > dout_clkcmu_hsi1_usbdrd 0 0 0 40000000 0 0 50000 Y ... > > Correct the clk_tree by adding correct clock parent for > "mout_hsi1_usbdrd_user". > > Post this change, clk_summary shows correct value. > > dout_shared2_div4 1 1 0 400000000 0 0 50000 Y ... > mout_clkcmu_hsi1_usbdrd 0 0 0 400000000 0 0 50000 Y ... > dout_clkcmu_hsi1_usbdrd 0 0 0 40000000 0 0 50000 Y ... > mout_hsi1_usbdrd_user 0 0 0 40000000 0 0 50000 Y ... > > Fixes: 485e13fe2fb6 ("clk: samsung: add top clock support for ExynosAuto v920 SoC") > Cc: stable <stable@kernel.org> Run checkpatch BEFORE you send the patches. WARNING: Invalid email format for stable: 'stable <stable@kernel.org>', prefer 'stable@kernel.org' Best regards, Krzysztof
On Tue, 06 May 2025 13:31:54 +0530, Pritam Manohar Sutar wrote: > clk_summary shows wrong value for "mout_hsi1_usbdrd_user". > It shows 400Mhz instead of 40Mhz as below. > > dout_shared2_div4 1 1 0 400000000 0 0 50000 Y ... > mout_hsi1_usbdrd_user 0 0 0 400000000 0 0 50000 Y ... > dout_clkcmu_hsi1_usbdrd 0 0 0 40000000 0 0 50000 Y ... > > [...] Applied, thanks! [1/1] clk: samsung: correct clock summary for hsi1 block https://git.kernel.org/krzk/linux/c/81214185e7e1fc6dfc8661a574c457accaf9a5a4 Best regards,
diff --git a/drivers/clk/samsung/clk-exynosautov920.c b/drivers/clk/samsung/clk-exynosautov920.c index dc8d4240f6de..b0561faecfeb 100644 --- a/drivers/clk/samsung/clk-exynosautov920.c +++ b/drivers/clk/samsung/clk-exynosautov920.c @@ -1393,7 +1393,7 @@ static const unsigned long hsi1_clk_regs[] __initconst = { /* List of parent clocks for Muxes in CMU_HSI1 */ PNAME(mout_hsi1_mmc_card_user_p) = {"oscclk", "dout_clkcmu_hsi1_mmc_card"}; PNAME(mout_hsi1_noc_user_p) = { "oscclk", "dout_clkcmu_hsi1_noc" }; -PNAME(mout_hsi1_usbdrd_user_p) = { "oscclk", "mout_clkcmu_hsi1_usbdrd" }; +PNAME(mout_hsi1_usbdrd_user_p) = { "oscclk", "dout_clkcmu_hsi1_usbdrd" }; PNAME(mout_hsi1_usbdrd_p) = { "dout_tcxo_div2", "mout_hsi1_usbdrd_user" }; static const struct samsung_mux_clock hsi1_mux_clks[] __initconst = {
clk_summary shows wrong value for "mout_hsi1_usbdrd_user". It shows 400Mhz instead of 40Mhz as below. dout_shared2_div4 1 1 0 400000000 0 0 50000 Y ... mout_hsi1_usbdrd_user 0 0 0 400000000 0 0 50000 Y ... dout_clkcmu_hsi1_usbdrd 0 0 0 40000000 0 0 50000 Y ... Correct the clk_tree by adding correct clock parent for "mout_hsi1_usbdrd_user". Post this change, clk_summary shows correct value. dout_shared2_div4 1 1 0 400000000 0 0 50000 Y ... mout_clkcmu_hsi1_usbdrd 0 0 0 400000000 0 0 50000 Y ... dout_clkcmu_hsi1_usbdrd 0 0 0 40000000 0 0 50000 Y ... mout_hsi1_usbdrd_user 0 0 0 40000000 0 0 50000 Y ... Fixes: 485e13fe2fb6 ("clk: samsung: add top clock support for ExynosAuto v920 SoC") Cc: stable <stable@kernel.org> Signed-off-by: Pritam Manohar Sutar <pritam.sutar@samsung.com> --- Changes in v2: - Updated commit message as pointed by Alim Akhtar. - Link to v1: https://patchwork.kernel.org/project/linux-samsung-soc/patch/20250428115049.2064955-1-pritam.sutar@samsung.com/ drivers/clk/samsung/clk-exynosautov920.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)