@@ -34,9 +34,14 @@
* see gen1/gen2 for detail
*/
enum rsnd_reg {
- /* SRU/SCU/SSIU */
+ /* SCU (SRC/SSIU/MIX/CTU/DVC) */
RSND_REG_SSI_MODE0,
RSND_REG_SSI_MODE1,
+ RSND_REG_SSI_CTRL, /* Gen2 only */
+ RSND_REG_SSI_BUSIF_MODE, /* Gen2 only */
+ RSND_REG_SSI_BUSIF_ADINR, /* Gen2 only */
+ RSND_REG_SSI_BUSIF_DALIGN, /* Gen2 only */
+ RSND_REG_SSI_INT_ENABLE, /* Gen2 only */
RSND_REG_SRC_BUSIF_MODE,
RSND_REG_SRC_ROUTE_MODE0,
RSND_REG_SRC_SWRSR,
@@ -45,9 +50,28 @@ enum rsnd_reg {
RSND_REG_SRC_IFSCR,
RSND_REG_SRC_IFSVR,
RSND_REG_SRC_SRCCR,
+ RSND_REG_SRC_CTRL, /* Gen2 only */
+ RSND_REG_SRC_BSDSR, /* Gen2 only */
+ RSND_REG_SRC_BSISR, /* Gen2 only */
+ RSND_REG_SRC_INT_ENABLE0, /* Gen2 only */
+ RSND_REG_SRC_BUSIF_DALIGN, /* Gen2 only */
+ RSND_REG_SRCIN_TIMSEL0, /* Gen2 only */
+ RSND_REG_SRCIN_TIMSEL1, /* Gen2 only */
+ RSND_REG_SRCIN_TIMSEL2, /* Gen2 only */
+ RSND_REG_SRCIN_TIMSEL3, /* Gen2 only */
+ RSND_REG_SRCIN_TIMSEL4, /* Gen2 only */
+ RSND_REG_SRCOUT_TIMSEL0, /* Gen2 only */
+ RSND_REG_SRCOUT_TIMSEL1, /* Gen2 only */
+ RSND_REG_SRCOUT_TIMSEL2, /* Gen2 only */
+ RSND_REG_SRCOUT_TIMSEL3, /* Gen2 only */
+ RSND_REG_SRCOUT_TIMSEL4, /* Gen2 only */
RSND_REG_SCU_SYS_STATUS0,
+ RSND_REG_SCU_SYS_STATUS1, /* Gen2 only */
RSND_REG_SCU_SYS_INT_EN0,
+ RSND_REG_SCU_SYS_INT_EN1, /* Gen2 only */
+ RSND_REG_CMD_CTRL, /* Gen2 only */
RSND_REG_CMD_ROUTE_SLCT,
+ RSND_REG_CMDOUT_TIMSEL, /* Gen2 only */
RSND_REG_CTU_CTUIR,
RSND_REG_CTU_ADINR,
RSND_REG_MIX_SWRSR,
@@ -68,13 +92,18 @@ enum rsnd_reg {
RSND_REG_DVC_VOL0R,
RSND_REG_DVC_VOL1R,
RSND_REG_DVC_DVUER,
+ RSND_REG_DVC_VRCTR, /* Gen2 only */
+ RSND_REG_DVC_VRPDR, /* Gen2 only */
+ RSND_REG_DVC_VRDBR, /* Gen2 only */
/* ADG */
RSND_REG_BRRA,
RSND_REG_BRRB,
RSND_REG_SSICKR,
+ RSND_REG_DIV_EN, /* Gen2 only */
RSND_REG_AUDIO_CLK_SEL0,
RSND_REG_AUDIO_CLK_SEL1,
+ RSND_REG_AUDIO_CLK_SEL2, /* Gen2 only */
/* SSI */
RSND_REG_SSICR,
@@ -83,71 +112,9 @@ enum rsnd_reg {
RSND_REG_SSIRDR,
RSND_REG_SSIWSR,
- /* SHARE see below */
- RSND_REG_SHARE01,
- RSND_REG_SHARE02,
- RSND_REG_SHARE03,
- RSND_REG_SHARE04,
- RSND_REG_SHARE05,
- RSND_REG_SHARE06,
- RSND_REG_SHARE07,
- RSND_REG_SHARE08,
- RSND_REG_SHARE09,
- RSND_REG_SHARE10,
- RSND_REG_SHARE11,
- RSND_REG_SHARE12,
- RSND_REG_SHARE13,
- RSND_REG_SHARE14,
- RSND_REG_SHARE15,
- RSND_REG_SHARE16,
- RSND_REG_SHARE17,
- RSND_REG_SHARE18,
- RSND_REG_SHARE19,
- RSND_REG_SHARE20,
- RSND_REG_SHARE21,
- RSND_REG_SHARE22,
- RSND_REG_SHARE23,
- RSND_REG_SHARE24,
- RSND_REG_SHARE25,
- RSND_REG_SHARE26,
- RSND_REG_SHARE27,
- RSND_REG_SHARE28,
- RSND_REG_SHARE29,
-
RSND_REG_MAX,
};
-/* Gen2 only */
-#define RSND_REG_SRC_CTRL RSND_REG_SHARE01
-#define RSND_REG_SSI_CTRL RSND_REG_SHARE02
-#define RSND_REG_SSI_BUSIF_MODE RSND_REG_SHARE03
-#define RSND_REG_SSI_BUSIF_ADINR RSND_REG_SHARE04
-#define RSND_REG_SSI_INT_ENABLE RSND_REG_SHARE05
-#define RSND_REG_SRC_BSDSR RSND_REG_SHARE06
-#define RSND_REG_SRC_BSISR RSND_REG_SHARE07
-#define RSND_REG_DIV_EN RSND_REG_SHARE08
-#define RSND_REG_SRCIN_TIMSEL0 RSND_REG_SHARE09
-#define RSND_REG_SRCIN_TIMSEL1 RSND_REG_SHARE10
-#define RSND_REG_SRCIN_TIMSEL2 RSND_REG_SHARE11
-#define RSND_REG_SRCIN_TIMSEL3 RSND_REG_SHARE12
-#define RSND_REG_SRCIN_TIMSEL4 RSND_REG_SHARE13
-#define RSND_REG_SRCOUT_TIMSEL0 RSND_REG_SHARE14
-#define RSND_REG_SRCOUT_TIMSEL1 RSND_REG_SHARE15
-#define RSND_REG_SRCOUT_TIMSEL2 RSND_REG_SHARE16
-#define RSND_REG_SRCOUT_TIMSEL3 RSND_REG_SHARE17
-#define RSND_REG_SRCOUT_TIMSEL4 RSND_REG_SHARE18
-#define RSND_REG_AUDIO_CLK_SEL2 RSND_REG_SHARE19
-#define RSND_REG_CMD_CTRL RSND_REG_SHARE20
-#define RSND_REG_CMDOUT_TIMSEL RSND_REG_SHARE21
-#define RSND_REG_SSI_BUSIF_DALIGN RSND_REG_SHARE22
-#define RSND_REG_DVC_VRCTR RSND_REG_SHARE23
-#define RSND_REG_DVC_VRPDR RSND_REG_SHARE24
-#define RSND_REG_DVC_VRDBR RSND_REG_SHARE25
-#define RSND_REG_SCU_SYS_STATUS1 RSND_REG_SHARE26
-#define RSND_REG_SCU_SYS_INT_EN1 RSND_REG_SHARE27
-#define RSND_REG_SRC_INT_ENABLE0 RSND_REG_SHARE28
-#define RSND_REG_SRC_BUSIF_DALIGN RSND_REG_SHARE29
-
struct rsnd_of_data;
struct rsnd_priv;
struct rsnd_mod;