| Message ID | 20170623183045.21494-3-ard.biesheuvel@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Platforms/AMD/Styx: various Cello related fixes | expand |
diff --git a/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc b/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc index ddb944d0beb4..d10c0901c811 100644 --- a/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc +++ b/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc @@ -404,6 +404,7 @@ DEFINE DO_KCS = 0 # gAmdStyxTokenSpaceGuid.PcdSata0PortCount|2 gAmdStyxTokenSpaceGuid.PcdSata1PortCount|0 + gAmdStyxTokenSpaceGuid.PcdSataPortMode|0xf # PCIe Support gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xF0000000 diff --git a/Platforms/AMD/Styx/Overdrive1000Board/Overdrive1000Board.dsc b/Platforms/AMD/Styx/Overdrive1000Board/Overdrive1000Board.dsc index f6d2d37014dd..298cf3eb1c28 100644 --- a/Platforms/AMD/Styx/Overdrive1000Board/Overdrive1000Board.dsc +++ b/Platforms/AMD/Styx/Overdrive1000Board/Overdrive1000Board.dsc @@ -406,6 +406,8 @@ DEFINE DO_KCS = 1 # gAmdStyxTokenSpaceGuid.PcdSata0PortCount|2 gAmdStyxTokenSpaceGuid.PcdSata1PortCount|0 + gAmdStyxTokenSpaceGuid.PcdSataPortMode|0xf + # PCIe Support gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xF0000000 diff --git a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc index 7ac3ce3760fa..d0b541f9bfa1 100644 --- a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc +++ b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc @@ -413,6 +413,7 @@ DEFINE DO_KCS = 1 # gAmdStyxTokenSpaceGuid.PcdSata0PortCount|8 gAmdStyxTokenSpaceGuid.PcdSata1PortCount|6 + gAmdStyxTokenSpaceGuid.PcdSataPortMode|0xfffffff # PCIe Support gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xF0000000
The SATA related PCDs consumed by AmdSataInitLib contain a PcdSataPortMode PCD that sets the port mode to all ports. This PCD defaults to zero, while the code in question has no default, i.e., the value 0 is not treated as either 1, 2 or 3, and so the init sequence is not carried out correctly. While observed SATA link detection issues on CelloBoard appear to be unrelated to this (i.e., this change did not improve the situation), let's set the correct values nonetheless. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> --- Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc | 1 + Platforms/AMD/Styx/Overdrive1000Board/Overdrive1000Board.dsc | 2 ++ Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc | 1 + 3 files changed, 4 insertions(+)