[RISU,11/11] aarch64.risu: update AdvancedSIMD across lanes

Message ID	20170704144859.17644-12-alex.bennee@linaro.org
State	New
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; From: =?utf-8?q?Alex_Benn=C3=A9e?= <alex.bennee@linaro.org> To: peter.maydell@linaro.org Date: Tue, 4 Jul 2017 15:48:59 +0100 Message-Id: <20170704144859.17644-12-alex.bennee@linaro.org> In-Reply-To: <20170704144859.17644-1-alex.bennee@linaro.org> References: <20170704144859.17644-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [RISU PATCH 11/11] aarch64.risu: update AdvancedSIMD across lanes Precedence: list Cc: qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= <alex.bennee@linaro.org>, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org>
Series	Misc fixes, documentation and patterns \| expand [RISU,00/11] Misc fixes, documentation and patterns [RISU,01/11] risu: make match status take tracing into account [RISU,02/11] reginfo.c: always return 1 on OP_TESTEND [RISU,03/11] README: document --static builds [RISU,04/11] README: document record/replay support [RISU,05/11] risu.el: derive from text-mode [RISU,06/11] risugen: fix bad indent [RISU,07/11] risugen: support @GroupName in risu files [RISU,08/11] aarch64.risu: document naming conventions [RISU,09/11] aarch64.risu: remove duplicate AdvSIMD Scalar 3 same block [RISU,10/11] aarch64.risu: remove duplicate AdvSIMD scalar 2 reg misc block [RISU,11/11] aarch64.risu: update AdvancedSIMD across lanes

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20170704144859.17644-12-alex.bennee@linaro.org

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From: =?utf-8?q?Alex_Benn=C3=A9e?= <alex.bennee@linaro.org>
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Date: Tue,  4 Jul 2017 15:48:59 +0100
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Subject: [Qemu-devel] [RISU PATCH 11/11] aarch64.risu: update AdvancedSIMD
	across lanes
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Series

Misc fixes, documentation and patterns | expand

Commit Message

Alex Bennée July 4, 2017, 2:48 p.m. UTC

- sorted alphabetically
 - aligned the instructions patterns
 - adding half-precision F[MAX|MIN][NMV|V]
 - add @AdvSIMDAcrossVector group

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>

---
 aarch64.risu | 90 +++++++++++++++++++++++++++++++++---------------------------
 1 file changed, 49 insertions(+), 41 deletions(-)

-- 
2.13.0

diff --git a/aarch64.risu b/aarch64.risu
index 5450cd3..215882e 100644
--- a/aarch64.risu
+++ b/aarch64.risu
@@ -1955,50 +1955,58 @@  ZIP2 A64_V 0 Q:1 001110 size:2 0 rm:5 0 111 10 rn:5 rd:5 \
 # ReservedValue: break the !($size == 3 && $Q == 0) constraint
 ZIP2_RES A64_V 0 0 001110 11 0 rm:5 0 111 10 rn:5 rd:5
 
-# C3.6.4 AdvSIMD across lanes
+# C4-286 AdvSIMD across vector lanes
 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16  12 11 10 9  5 4  0
 #  0  Q  U  0  1  1  1  0  size  1  1  0  0  0 opcode  1  0  Rn   Rd
+@AdvSIMDAcrossVector
+
+ADDV         A64_V 0 Q:1 0 01110 s:2 11000 11011 10 rn:5 rd:5 \
+!constraints { $s < 2 || ($s == 2 && $Q == 1); }
+# ReservedValue: break the constraint (s==2) => (Q=1)
+ADDV_RES     A64_V 0  0  0 01110  10 11000 11011 10 rn:5 rd:5
+
+FMAXNMV      A64_V 0  1  1 01110  00 11000 01100 10 rn:5 rd:5
+FMAXV        A64_V 0  1  1 01110  00 11000 01111 10 rn:5 rd:5
+FMINNMV      A64_V 0  1  1 01110  10 11000 01100 10 rn:5 rd:5
+FMINV        A64_V 0  1  1 01110  10 11000 01111 10 rn:5 rd:5
+
+# ARMv8.2 Half-precision variants
+FMAXNMV_FP16 A64_V 0 q:1 0 01110  00 11000 01100 10 rn:5 rd:5
+FMAXV_FP16   A64_V 0 q:1 0 01110  00 11000 01111 10 rn:5 rd:5
+FMINNMV_FP16 A64_V 0 q:1 0 01110  10 11000 01100 10 rn:5 rd:5
+FMINV_FP16   A64_V 0 q:1 0 01110  10 11000 01111 10 rn:5 rd:5
+
+SADDLV       A64_V 0 Q:1 0 01110 s:2 11000 00011 10 rn:5 rd:5 \
+!constraints { $s < 2 || ($s == 2 && $Q == 1); }
+# ReservedValue: break the constraint (s==2) => (Q=1)
+SADDLV_RES   A64_V 0   0 0 01110  10 11000 00011 10 rn:5 rd:5
+
+SMAXV        A64_V 0 Q:1 0 01110 s:2 11000 01010 10 rn:5 rd:5 \
+!constraints { $s < 2 || ($s == 2 && $Q == 1); }
+# ReservedValue: break the constraint (s==2) => (Q=1)
+SMAXV_RES    A64_V 0   0 0 01110  10 11000 01010 10 rn:5 rd:5
+
+SMINV        A64_V 0 Q:1 0 01110 s:2 11000 11010 10 rn:5 rd:5 \
+!constraints { $s < 2 || ($s == 2 && $Q == 1); }
+# ReservedValue: break the constraint (s==2) => (Q=1)
+SMINV_RES    A64_V 0   0 0 01110  10 11000 11010 10 rn:5 rd:5
+
+UADDLV       A64_V 0 Q:1 1 01110 s:2 11000 00011 10 rn:5 rd:5 \
+!constraints { $s < 2 || ($s == 2 && $Q == 1); }
+# ReservedValue: break the constraint (s==2) => (Q=1)
+UADDLV_RES   A64_V 0   0 1 01110  10 11000 00011 10 rn:5 rd:5
+
+UMAXV        A64_V 0 Q:1 1 01110 s:2 11000 01010 10 rn:5 rd:5 \
+!constraints { $s < 2 || ($s == 2 && $Q == 1); }
+# ReservedValue: break the constraint (s==2) => (Q=1)
+UMAXV_RES    A64_V 0   0 1 01110  10 11000 01010 10 rn:5 rd:5
+
+UMINV        A64_V 0 Q:1 1 01110 s:2 11000 11010 10 rn:5 rd:5 \
+!constraints { $s < 2 || ($s == 2 && $Q == 1); }
+# ReservedValue: break the constraint (s==2) => (Q=1)
+UMINV_RES    A64_V 0   0 1 01110  10 11000 11010 10 rn:5 rd:5
 
-SADDLV A64_V 0 Q:1 0 01110 size:2 11000 00011 10 rn:5 rd:5 \
-!constraints { $size < 2 || ($size == 2 && $Q == 1); }
-# ReservedValue: break the constraint (size==2) => (Q=1)
-SADDLV_RES A64_V 0 0 0 01110 10 11000 00011 10 rn:5 rd:5
-
-SMAXV A64_V 0 Q:1 0 01110 size:2 11000 01010 10 rn:5 rd:5 \
-!constraints { $size < 2 || ($size == 2 && $Q == 1); }
-# ReservedValue: break the constraint (size==2) => (Q=1)
-SMAXV_RES A64_V 0 0 0 01110 10 11000 01010 10 rn:5 rd:5
-
-SMINV A64_V 0 Q:1 0 01110 size:2 11000 11010 10 rn:5 rd:5 \
-!constraints { $size < 2 || ($size == 2 && $Q == 1); }
-# ReservedValue: break the constraint (size==2) => (Q=1)
-SMINV_RES A64_V 0 0 0 01110 10 11000 11010 10 rn:5 rd:5
-
-ADDV A64_V 0 Q:1 0 01110 size:2 11000 11011 10 rn:5 rd:5 \
-!constraints { $size < 2 || ($size == 2 && $Q == 1); }
-# ReservedValue: break the constraint (size==2) => (Q=1)
-ADDV_RES A64_V 0 0 0 01110 10 11000 11011 10 rn:5 rd:5
-
-UADDLV A64_V 0 Q:1 1 01110 size:2 11000 00011 10 rn:5 rd:5 \
-!constraints { $size < 2 || ($size == 2 && $Q == 1); }
-# ReservedValue: break the constraint (size==2) => (Q=1)
-UADDLV_RES A64_V 0 0 1 01110 10 11000 00011 10 rn:5 rd:5
-
-UMAXV A64_V 0 Q:1 1 01110 size:2 11000 01010 10 rn:5 rd:5 \
-!constraints { $size < 2 || ($size == 2 && $Q == 1); }
-# ReservedValue: break the constraint (size==2) => (Q=1)
-UMAXV_RES A64_V 0 0 1 01110 10 11000 01010 10 rn:5 rd:5
-
-UMINV A64_V 0 Q:1 1 01110 size:2 11000 11010 10 rn:5 rd:5 \
-!constraints { $size < 2 || ($size == 2 && $Q == 1); }
-# ReservedValue: break the constraint (size==2) => (Q=1)
-UMINV_RES A64_V 0 0 1 01110 10 11000 11010 10 rn:5 rd:5
-
-FMAXNMV A64_V 0 1 1 01110 00 11000 01100 10 rn:5 rd:5
-FMAXV A64_V 0 1 1 01110 00 11000 01111 10 rn:5 rd:5
-
-FMINNMV A64_V 0 1 1 01110 10 11000 01100 10 rn:5 rd:5
-FMINV A64_V 0 1 1 01110 10 11000 01111 10 rn:5 rd:5
+@
 
 # C3.6.5 AdvSIMD copy
 # 31 30 29 28 27 26 25 24 23 22 21 20    16 15 14    11 10 9  5 4  0

[RISU,11/11] aarch64.risu: update AdvancedSIMD across lanes

Commit Message

Patch