diff mbox series

[v1,1/3] example: ipfragaddress: fix compilation with clang

Message ID 1499860815-9962-2-git-send-email-odpbot@yandex.ru
State New
Headers show
Series [v1,1/3] example: ipfragaddress: fix compilation with clang | expand

Commit Message

Github ODP bot July 12, 2017, noon UTC 
From: Dmitry Eremin-Solenikov <dmitry.ereminsolenikov@linaro.org>


Clang 3.8 is stricter than GCC wrt register allocation vs 128-bit
variables. Sometimes it can not understand using 128-bit var in place of
64-bit register resulting in the following errors:

/odp_ipfragreass_atomics_arm.h:18:51: error: value size does not match
register
      size specified by the constraint and modifier
      [-Werror,-Wasm-operand-widths]
                __asm__ volatile("ldaxp %0, %H0, [%1]" : "=&r" (old)
                                                                ^
./odp_ipfragreass_atomics_arm.h:18:27: note: use constraint modifier "w"
                __asm__ volatile("ldaxp %0, %H0, [%1]" : "=&r" (old)

Explicitly pass low and high parts of 128-bit variable in separate
assembly parameters.

Signed-off-by: Dmitry Eremin-Solenikov <dmitry.ereminsolenikov@linaro.org>

---
/** Email created from pull request 73 (lumag:cross-2)
 ** https://github.com/Linaro/odp/pull/73
 ** Patch: https://github.com/Linaro/odp/pull/73.patch
 ** Base sha: 7fc6d27e937b57b31360b07028388c811f8300dc
 ** Merge commit sha: a4eb9d1fce06d324ea13633a5df60a00640673c8
 **/
 example/ipfragreass/odp_ipfragreass_atomics_arm.h | 21 ++++++++++++++-------
 1 file changed, 14 insertions(+), 7 deletions(-)
diff mbox series

Patch

diff --git a/example/ipfragreass/odp_ipfragreass_atomics_arm.h b/example/ipfragreass/odp_ipfragreass_atomics_arm.h
index 99c37a77..d848ee6f 100644
--- a/example/ipfragreass/odp_ipfragreass_atomics_arm.h
+++ b/example/ipfragreass/odp_ipfragreass_atomics_arm.h
@@ -13,26 +13,33 @@ 
 static inline __int128 lld(__int128 *var, int mo)
 {
 	__int128 old;
+	uint64_t lo, hi;
 
 	if (mo == __ATOMIC_ACQUIRE)
-		__asm__ volatile("ldaxp %0, %H0, [%1]" : "=&r" (old)
+		__asm__ volatile("ldaxp %0, %1, [%2]" : "=r" (lo), "=r" (hi)
 				 : "r" (var) : "memory");
 	else /* mo == __ATOMIC_RELAXED */
-		__asm__ volatile("ldxp %0, %H0, [%1]" : "=&r" (old)
+		__asm__ volatile("ldxp %0, %1, [%2]" : "=r" (lo), "=r" (hi)
 				 : "r" (var) : );
+	old = hi;
+	old <<= 64;
+	old |= lo;
+
 	return old;
+
 }
 
 static inline uint32_t scd(__int128 *var, __int128 neu, int mo)
 {
 	uint32_t ret;
+	uint64_t lo = neu, hi = neu >> 64;
 
 	if (mo == __ATOMIC_RELEASE)
-		__asm__ volatile("stlxp %w0, %1, %H1, [%2]" : "=&r" (ret)
-				 : "r" (neu), "r" (var) : "memory");
+		__asm__ volatile("stlxp %w0, %1, %2, [%3]" : "=&r" (ret)
+				 : "r" (lo), "r" (hi), "r" (var) : "memory");
 	else /* mo == __ATOMIC_RELAXED */
-		__asm__ volatile("stxp %w0, %1, %H1, [%2]" : "=&r" (ret)
-				 : "r" (neu), "r" (var) : );
+		__asm__ volatile("stxp %w0, %1, %2, [%3]" : "=&r" (ret)
+				 : "r" (lo), "r" (hi), "r" (var) : "memory");
 	return ret;
 }
 
@@ -81,7 +88,7 @@  static inline uint32_t scd(uint64_t *var, uint64_t neu, int mo)
 
 	if (mo == __ATOMIC_RELEASE)
 		__asm__ volatile("dmb ish" ::: "memory");
-	__asm__ volatile("strexd %0, %1, %H1, [%2]" : "=&r" (ret)
+	__asm__ volatile("strexd %0, %L1, %H1, [%2]" : "=&r" (ret)
 			 : "r" (neu), "r" (var) : );
 	return ret;
 }