@@ -22,6 +22,21 @@
#define LPAE_SH_INNER 0x3
/*
+ * Attribute Indexes.
+ *
+ * These are valid in the AttrIndx[2:0] field of an LPAE stage 1 page
+ * table entry. They are indexes into the bytes of the MAIR*
+ * registers, as defined below.
+ *
+ */
+#define MT_DEVICE_nGnRnE 0x0
+#define MT_NORMAL_NC 0x1
+#define MT_NORMAL_WT 0x2
+#define MT_NORMAL_WB 0x3
+#define MT_DEVICE_nGnRE 0x4
+#define MT_NORMAL 0x7
+
+/*
* LPAE Memory region attributes. Indexed by the AttrIndex bits of a
* LPAE entry; the 8-bit fields are packed little-endian into MAIR0 and MAIR1.
*
@@ -38,24 +53,17 @@
* reserved 110
* MT_NORMAL 111 1111 1111 -- Write-back write-allocate
*/
-#define MAIR0VAL 0xeeaa4400
-#define MAIR1VAL 0xff000004
-#define MAIRVAL (MAIR0VAL|MAIR1VAL<<32)
+#define MAIR(attr, mt) (_AC(attr, ULL) << ((mt) * 8))
-/*
- * Attribute Indexes.
- *
- * These are valid in the AttrIndx[2:0] field of an LPAE stage 1 page
- * table entry. They are indexes into the bytes of the MAIR*
- * registers, as defined above.
- *
- */
-#define MT_DEVICE_nGnRnE 0x0
-#define MT_NORMAL_NC 0x1
-#define MT_NORMAL_WT 0x2
-#define MT_NORMAL_WB 0x3
-#define MT_DEVICE_nGnRE 0x4
-#define MT_NORMAL 0x7
+#define MAIRVAL (MAIR(0x00, MT_DEVICE_nGnRnE)| \
+ MAIR(0x44, MT_NORMAL_NC) | \
+ MAIR(0xaa, MT_NORMAL_WT) | \
+ MAIR(0xee, MT_NORMAL_WB) | \
+ MAIR(0x04, MT_DEVICE_nGnRE) | \
+ MAIR(0xff, MT_NORMAL))
+
+#define MAIR0VAL (MAIRVAL & 0xffffffff)
+#define MAIR1VAL (MAIRVAL >> 32)
#define PAGE_HYPERVISOR (MT_NORMAL)
#define PAGE_HYPERVISOR_NOCACHE (MT_DEVICE_nGnRE)