[V2,6/8] musl: Disable thumb1 ISA

Message ID	20171115034342.42901-2-raj.khem@gmail.com
State	Superseded
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: best guess record for domain of openembedded-core-bounces@lists.openembedded.org designates 140.211.169.62 as permitted sender) client-ip=140.211.169.62; From: Khem Raj <raj.khem@gmail.com> To: openembedded-core@lists.openembedded.org Date: Tue, 14 Nov 2017 19:43:42 -0800 Message-Id: <20171115034342.42901-2-raj.khem@gmail.com> In-Reply-To: <20171115034342.42901-1-raj.khem@gmail.com> References: <20171115034342.42901-1-raj.khem@gmail.com> Subject: [OE-core] [PATCH V2 6/8] musl: Disable thumb1 ISA Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: openembedded-core-bounces@lists.openembedded.org Errors-To: openembedded-core-bounces@lists.openembedded.org
Series	None \| expand [V2,2/8] binutils: update to 2.29.1 [V2,6/8] musl: Disable thumb1 ISA

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20171115034342.42901-2-raj.khem@gmail.com

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From: Khem Raj <raj.khem@gmail.com>
To: openembedded-core@lists.openembedded.org
Date: Tue, 14 Nov 2017 19:43:42 -0800
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Subject: [OE-core] [PATCH V2 6/8] musl: Disable thumb1 ISA
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Commit Message

Khem Raj Nov. 15, 2017, 3:43 a.m. UTC

From: Andrea Adami <andrea.adami@gmail.com>


thumb1 is unsupported see http://www.openwall.com/lists/musl/2017/10/20/10

Fix
[YOCTO #12336]

Signed-off-by: Andrea Adami <andrea.adami@gmail.com>

Signed-off-by: Khem Raj <raj.khem@gmail.com>

---
Changes in V2: Add author attribution

 meta/recipes-core/musl/musl.inc | 5 +++++
 1 file changed, 5 insertions(+)

-- 
2.15.0

-- 
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diff --git a/meta/recipes-core/musl/musl.inc b/meta/recipes-core/musl/musl.inc
index 56c9d7fe17..9af1172ae0 100644
--- a/meta/recipes-core/musl/musl.inc
+++ b/meta/recipes-core/musl/musl.inc
@@ -26,3 +26,8 @@  INSANE_SKIP_${PN} = "dev-so"
 # Doesn't compile in MIPS16e mode due to use of hand-written
 # assembly
 MIPS_INSTRUCTION_SET = "mips"
+
+# thumb1 is unsupported
+ARM_INSTRUCTION_SET_armv5 = "arm"
+ARM_INSTRUCTION_SET_armv4 = "arm"
+