[v2,08/19] ARM: dts: aspeed: Add clock phandle to GPIO

Message ID	20171215062443.23059-9-joel@jms.id.au
State	Superseded
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; From: Joel Stanley <joel@jms.id.au> To: Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>, Arnd Bergmann <arnd@arndb.de>, Andrew Jeffery <andrew@aj.id.au>, Patrick Venture <venture@google.com>, Xo Wang <xow@google.com>, Lei YU <mine260309@gmail.com> Cc: =?utf-8?q?C=C3=A9dric_Le_Goater?= <clg@kaod.org>, Benjamin Herrenschmidt <benh@kernel.crashing.org>, Jeremy Kerr <jk@ozlabs.org>, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-aspeed@lists.ozlabs.org Subject: [PATCH v2 08/19] ARM: dts: aspeed: Add clock phandle to GPIO Date: Fri, 15 Dec 2017 16:54:32 +1030 Message-Id: <20171215062443.23059-9-joel@jms.id.au> In-Reply-To: <20171215062443.23059-1-joel@jms.id.au> References: <20171215062443.23059-1-joel@jms.id.au> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk
Series	None \| expand [v2,02/19] dt-bindings: gpio: Add ASPEED constants [v2,03/19] ARM: dts: aspeed: Add LPC and child devices [v2,04/19] ARM: dts: aspeed: Add proper clock references [v2,05/19] ARM: dts: aspeed: Add MAC clocks [v2,06/19] ARM: dts: aspeed: Add watchdog clocks [v2,07/19] ARM: dts: aspeed: Add flash controller clocks [v2,08/19] ARM: dts: aspeed: Add clock phandle to GPIO [v2,10/19] ARM: dts: aspeed: Add LPC Snoop device [v2,11/19] ARM: dts: aspeed: Remove skeleton.dtsi [v2,12/19] ARM: dts: aspeed: Update license headers [v2,13/19] ARM: dts: Add OpenBMC flash layout [v2,15/19] ARM: dts: aspeed: Add Witherspoon BMC machine [v2,16/19] ARM: dts: aspeed: Add Ingrasys Zaius BMC machine [v2,17/19] ARM: dts: aspeed: Add Qanta Q71L BMC machine [v2,18/19] ARM: dts: aspeed-romulus: Update Romulus system [v2,19/19] ARM: dts: aspeed-plametto: Add flash layout

Message ID

20171215062443.23059-9-joel@jms.id.au

State

Superseded

Headers

Received-SPF: pass (google.com: best guess record for domain of
	linux-kernel-owner@vger.kernel.org designates 209.132.180.67
	as permitted sender) client-ip=209.132.180.67; 
From: Joel Stanley <joel@jms.id.au>
To: Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>,
	Arnd Bergmann <arnd@arndb.de>, Andrew Jeffery <andrew@aj.id.au>,
	Patrick Venture <venture@google.com>, Xo Wang <xow@google.com>,
	Lei YU <mine260309@gmail.com>
Cc: =?utf-8?q?C=C3=A9dric_Le_Goater?= <clg@kaod.org>,
	Benjamin Herrenschmidt <benh@kernel.crashing.org>, Jeremy Kerr
	<jk@ozlabs.org>, devicetree@vger.kernel.org, 
	linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, 
	linux-aspeed@lists.ozlabs.org
Subject: [PATCH v2 08/19] ARM: dts: aspeed: Add clock phandle to GPIO
Date: Fri, 15 Dec 2017 16:54:32 +1030
Message-Id: <20171215062443.23059-9-joel@jms.id.au>
In-Reply-To: <20171215062443.23059-1-joel@jms.id.au>
References: <20171215062443.23059-1-joel@jms.id.au>
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk

Series

None | expand

Commit Message

Joel Stanley Dec. 15, 2017, 6:24 a.m. UTC

This enables a feature where the driver can debounce inputs.

Signed-off-by: Joel Stanley <joel@jms.id.au>

---
 arch/arm/boot/dts/aspeed-g4.dtsi | 1 +
 arch/arm/boot/dts/aspeed-g5.dtsi | 1 +
 2 files changed, 2 insertions(+)

-- 
2.14.1

diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index afac0ca0cb10..fa52a01f50b5 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -144,6 +144,7 @@ 
 				reg = <0x1e780000 0x1000>;
 				interrupts = <20>;
 				gpio-ranges = <&pinctrl 0 0 220>;
+				clocks = <&syscon ASPEED_CLK_APB>;
 				interrupt-controller;
 			};
 
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index f3689caf6fe2..5e6db2aa5c23 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -187,6 +187,7 @@ 
 				reg = <0x1e780000 0x1000>;
 				interrupts = <20>;
 				gpio-ranges = <&pinctrl 0 0 220>;
+				clocks = <&syscon ASPEED_CLK_APB>;
 				interrupt-controller;
 			};

[v2,08/19] ARM: dts: aspeed: Add clock phandle to GPIO

Commit Message

Patch