[v3,07/20] ARM: dts: aspeed: Add flash controller clocks

Message ID	20171220032328.30584-8-joel@jms.id.au
State	Accepted
Commit	e1e0ec419c5c18170fec18a32daab75b5b690aba
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; From: Joel Stanley <joel@jms.id.au> To: Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>, Arnd Bergmann <arnd@arndb.de>, Andrew Jeffery <andrew@aj.id.au>, Patrick Venture <venture@google.com>, Xo Wang <xow@google.com>, Lei YU <mine260309@gmail.com> Cc: =?utf-8?q?C=C3=A9dric_Le_Goater?= <clg@kaod.org>, Benjamin Herrenschmidt <benh@kernel.crashing.org>, Jeremy Kerr <jk@ozlabs.org>, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-aspeed@lists.ozlabs.org Subject: [PATCH v3 07/20] ARM: dts: aspeed: Add flash controller clocks Date: Wed, 20 Dec 2017 13:53:15 +1030 Message-Id: <20171220032328.30584-8-joel@jms.id.au> In-Reply-To: <20171220032328.30584-1-joel@jms.id.au> References: <20171220032328.30584-1-joel@jms.id.au> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk
Series	None \| expand [v3,02/20] dt-bindings: gpio: Add ASPEED constants [v3,05/20] ARM: dts: aspeed: Add MAC clocks [v3,06/20] ARM: dts: aspeed: Add watchdog clocks [v3,07/20] ARM: dts: aspeed: Add flash controller clocks [v3,08/20] ARM: dts: aspeed: Add clock phandle to GPIO [v3,09/20] ARM: dts: aspeed: Add PWM and tachometer node [v3,10/20] ARM: dts: aspeed: Add LPC Snoop device [v3,11/20] ARM: dts: aspeed: Remove skeleton.dtsi [v3,12/20] ARM: dts: aspeed: Update license headers [v3,13/20] ARM: dts: Add OpenBMC flash layout [v3,14/20] ARM: dts: aspeed: Sort ASPEED entries in makefile [v3,15/20] ARM: dts: aspeed: Add Witherspoon BMC machine [v3,16/20] ARM: dts: aspeed: Add Ingrasys Zaius BMC machine [v3,17/20] ARM: dts: aspeed: Add Qanta Q71L BMC machine [v3,18/20] ARM: dts: aspeed-romulus: Update Romulus system

Message ID

20171220032328.30584-8-joel@jms.id.au

State

Accepted

Commit

e1e0ec419c5c18170fec18a32daab75b5b690aba

Headers

Received-SPF: pass (google.com: best guess record for domain of
	linux-kernel-owner@vger.kernel.org designates 209.132.180.67
	as permitted sender) client-ip=209.132.180.67; 
From: Joel Stanley <joel@jms.id.au>
To: Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>,
	Arnd Bergmann <arnd@arndb.de>, Andrew Jeffery <andrew@aj.id.au>,
	Patrick Venture <venture@google.com>, Xo Wang <xow@google.com>,
	Lei YU <mine260309@gmail.com>
Cc: =?utf-8?q?C=C3=A9dric_Le_Goater?= <clg@kaod.org>,
	Benjamin Herrenschmidt <benh@kernel.crashing.org>, Jeremy Kerr
	<jk@ozlabs.org>, devicetree@vger.kernel.org, 
	linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, 
	linux-aspeed@lists.ozlabs.org
Subject: [PATCH v3 07/20] ARM: dts: aspeed: Add flash controller clocks
Date: Wed, 20 Dec 2017 13:53:15 +1030
Message-Id: <20171220032328.30584-8-joel@jms.id.au>
In-Reply-To: <20171220032328.30584-1-joel@jms.id.au>
References: <20171220032328.30584-1-joel@jms.id.au>
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk

Series

None | expand

Commit Message

Joel Stanley Dec. 20, 2017, 3:23 a.m. UTC

Reviewed-by: Cédric Le Goater <clg@kaod.org>

Signed-off-by: Joel Stanley <joel@jms.id.au>

---
 arch/arm/boot/dts/aspeed-g4.dtsi | 2 ++
 arch/arm/boot/dts/aspeed-g5.dtsi | 3 +++
 2 files changed, 5 insertions(+)

-- 
2.15.1

diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index 2b1bb31ce390..36cb66d8cc10 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -55,6 +55,7 @@ 
 			#address-cells = <1>;
 			#size-cells = <0>;
 			compatible = "aspeed,ast2400-fmc";
+			clocks = <&syscon ASPEED_CLK_AHB>;
 			status = "disabled";
 			interrupts = <19>;
 			flash@0 {
@@ -70,6 +71,7 @@ 
 			#address-cells = <1>;
 			#size-cells = <0>;
 			compatible = "aspeed,ast2400-spi";
+			clocks = <&syscon ASPEED_CLK_AHB>;
 			status = "disabled";
 			flash@0 {
 				reg = < 0 >;
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index 95bb04e4cee2..156b345ff20d 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -55,6 +55,7 @@ 
 			#address-cells = <1>;
 			#size-cells = <0>;
 			compatible = "aspeed,ast2500-fmc";
+			clocks = <&syscon ASPEED_CLK_AHB>;
 			status = "disabled";
 			interrupts = <19>;
 			flash@0 {
@@ -80,6 +81,7 @@ 
 			#address-cells = <1>;
 			#size-cells = <0>;
 			compatible = "aspeed,ast2500-spi";
+			clocks = <&syscon ASPEED_CLK_AHB>;
 			status = "disabled";
 			flash@0 {
 				reg = < 0 >;
@@ -99,6 +101,7 @@ 
 			#address-cells = <1>;
 			#size-cells = <0>;
 			compatible = "aspeed,ast2500-spi";
+			clocks = <&syscon ASPEED_CLK_AHB>;
 			status = "disabled";
 			flash@0 {
 				reg = < 0 >;

[v3,07/20] ARM: dts: aspeed: Add flash controller clocks

Commit Message

Patch