@@ -137,7 +137,7 @@ trap_##trap: \
.align 5
GLOBAL(hyp_traps_vector)
- .word 0 /* 0x00 - Reset */
+ b trap_reset /* 0x00 - Reset */
b trap_undefined_instruction /* 0x04 - Undefined Instruction */
b trap_hypervisor_call /* 0x08 - Hypervisor Call */
b trap_prefetch_abort /* 0x0c - Prefetch Abort */
@@ -146,6 +146,7 @@ GLOBAL(hyp_traps_vector)
b trap_irq /* 0x18 - IRQ */
b trap_fiq /* 0x1c - FIQ */
+DEFINE_TRAP_ENTRY(reset)
DEFINE_TRAP_ENTRY(undefined_instruction)
DEFINE_TRAP_ENTRY(hypervisor_call)
DEFINE_TRAP_ENTRY(prefetch_abort)
@@ -23,6 +23,11 @@
#include <asm/processor.h>
+void do_trap_reset(struct cpu_user_regs *regs)
+{
+ do_unexpected_trap("Reset", regs);
+}
+
void do_trap_undefined_instruction(struct cpu_user_regs *regs)
{
uint32_t pc = regs->pc;
At the moment, the reset vector is defined as .word 0 (e.g andeq r0, r0, r0). This is rather unintuitive and will result to execute the trap undefined. Instead introduce trap helpers for reset and will generate an error message in the unlikely case that reset will be called. This is part of XSA-254. Signed-off-by: Julien Grall <julien.grall@linaro.org> --- Changes in v2: - Replace .word 0 by trap_reset --- xen/arch/arm/arm32/entry.S | 3 ++- xen/arch/arm/arm32/traps.c | 5 +++++ 2 files changed, 7 insertions(+), 1 deletion(-)