| Message ID | 20180223154613.2096-4-alex.bennee@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | Group support and random clean-ups | expand |
On 23 February 2018 at 15:46, Alex Bennée <alex.bennee@linaro.org> wrote: > Signed-off-by: Alex Bennée <alex.bennee@linaro.org> > --- > aarch64.risu | 32 ++++++++++++++++++++++++++++++++ > 1 file changed, 32 insertions(+) > > diff --git a/aarch64.risu b/aarch64.risu > index 838bded..06a9f3c 100644 > --- a/aarch64.risu > +++ b/aarch64.risu > @@ -2937,3 +2937,35 @@ FCVTZUsi_RES A64_V sf:1 0011110 1 type:1 1 11 001 000000 rn:5 rd:5 > # End of: > # Data processing - SIMD and floating point > # Data processing - Scalar Floating-Point and Advanced SIMD > + > +# These are optional ARMv8.2 cryptographic extensions > +@v8.2,Cryptographic,CryptographicSHA > + > +# Cryptographic three-register SHA 512 > +# 31 21 20 16 15 14 13 12 11 10 9 5 4 0 > +# 11001110011 Rm 1 O 0 0 opcode Rn Rd > + > +SHA512H A64_V 1100 1110 011 rm:5 1 0 00 00 rn:5 rd:5 > +SHA512H2 A64_V 1100 1110 011 rm:5 1 0 00 01 rn:5 rd:5 > +SHA512SUI A64_V 1100 1110 011 rm:5 1 0 00 10 rn:5 rd:5 "SHA512SU1" > +RAX1 A64_V 1100 1110 011 rm:5 1 0 00 11 rn:5 rd:5 > +SM3PARTW1 A64_V 1100 1110 011 rm:5 1 1 00 00 rn:5 rd:5 > +SM3PARTW2 A64_V 1100 1110 011 rm:5 1 1 00 01 rn:5 rd:5 > +SM4 A64_V 1100 1110 011 rm:5 1 1 00 10 rn:5 rd:5 "SM4EKEY" I also had a pattern for the unallocated encoding: # unallocated encoding: O=1 opcode=11 SHA512_RES A64_C82 11001110011 rm:5 1 1 00 11 rn:5 rd:5 > + > +# Cryptographic four-register > +# 31 23 22 21 20 16 15 14 10 9 5 4 0 > +# 1100 1110 0 Op0 Rm 0 Ra Rn Rd > + > +EOR3 A64_V 1110 1110 0 00 rm:5 0 ra:5 rn:5 rd:5 > +BCAX A64_V 1110 1110 0 01 rm:5 0 ra:5 rn:5 rd:5 > +SM3SS1 A64_V 1110 1110 0 10 rm:5 0 ra:5 rn:5 rd:5 and another unallocated pattern: # unallocated: op0=11 C4REG_RES A64_C82 110011100 11 rm:5 0 ra:5 rn:5 rd:5 > +# Cryptographic two-register SHA 512 > +# 31 12 11 10 9 5 4 0 > +# 1100 1110 1100 0000 1000 op Rn Rd > + > +SHA512SU0 A64_V 1100 1110 1100 0000 1000 00 rn:5 rd:5 > +SM4E A64_V 1100 1110 1100 0000 1000 01 rn:5 rd:5 and again: # unallocated: opcode = 1x C2REG_RES A64_C82 1100 1110 1100 0000 1000 1 x:1 rn:5 rd:5 and I think you're missing these two lots of insns: # Cryptographic three-register, imm2 SM3TT1A A64_C82 11001110010 rm:5 10 imm:2 00 rn:5 rd:5 SM3TT1B A64_C82 11001110010 rm:5 10 imm:2 01 rn:5 rd:5 SM3TT2A A64_C82 11001110010 rm:5 10 imm:2 10 rn:5 rd:5 SM3TT2B A64_C82 11001110010 rm:5 10 imm:2 11 rn:5 rd:5 # XAR XAR A64_C82 1100 1110 100 rm:5 imm:6 rn:5 rd:5 thanks -- PMM
diff --git a/aarch64.risu b/aarch64.risu index 838bded..06a9f3c 100644 --- a/aarch64.risu +++ b/aarch64.risu @@ -2937,3 +2937,35 @@ FCVTZUsi_RES A64_V sf:1 0011110 1 type:1 1 11 001 000000 rn:5 rd:5 # End of: # Data processing - SIMD and floating point # Data processing - Scalar Floating-Point and Advanced SIMD + +# These are optional ARMv8.2 cryptographic extensions +@v8.2,Cryptographic,CryptographicSHA + +# Cryptographic three-register SHA 512 +# 31 21 20 16 15 14 13 12 11 10 9 5 4 0 +# 11001110011 Rm 1 O 0 0 opcode Rn Rd + +SHA512H A64_V 1100 1110 011 rm:5 1 0 00 00 rn:5 rd:5 +SHA512H2 A64_V 1100 1110 011 rm:5 1 0 00 01 rn:5 rd:5 +SHA512SUI A64_V 1100 1110 011 rm:5 1 0 00 10 rn:5 rd:5 +RAX1 A64_V 1100 1110 011 rm:5 1 0 00 11 rn:5 rd:5 +SM3PARTW1 A64_V 1100 1110 011 rm:5 1 1 00 00 rn:5 rd:5 +SM3PARTW2 A64_V 1100 1110 011 rm:5 1 1 00 01 rn:5 rd:5 +SM4 A64_V 1100 1110 011 rm:5 1 1 00 10 rn:5 rd:5 + +# Cryptographic four-register +# 31 23 22 21 20 16 15 14 10 9 5 4 0 +# 1100 1110 0 Op0 Rm 0 Ra Rn Rd + +EOR3 A64_V 1110 1110 0 00 rm:5 0 ra:5 rn:5 rd:5 +BCAX A64_V 1110 1110 0 01 rm:5 0 ra:5 rn:5 rd:5 +SM3SS1 A64_V 1110 1110 0 10 rm:5 0 ra:5 rn:5 rd:5 + +# Cryptographic two-register SHA 512 +# 31 12 11 10 9 5 4 0 +# 1100 1110 1100 0000 1000 op Rn Rd + +SHA512SU0 A64_V 1100 1110 1100 0000 1000 00 rn:5 rd:5 +SM4E A64_V 1100 1110 1100 0000 1000 01 rn:5 rd:5 + +@
Signed-off-by: Alex Bennée <alex.bennee@linaro.org> --- aarch64.risu | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) -- 2.15.1