| Message ID | 1353422034-28107-2-git-send-email-lee.jones@linaro.org |
|---|---|
| State | New |
| Headers | show |
diff --git a/arch/arm/cpu/armv7/u8500/timer.c b/arch/arm/cpu/armv7/u8500/timer.c index 79aad99..40326d8 100644 --- a/arch/arm/cpu/armv7/u8500/timer.c +++ b/arch/arm/cpu/armv7/u8500/timer.c @@ -70,7 +70,7 @@ struct u8500_mtu { * The MTU is clocked at 133 MHz by default. (V1 and later) */ #define TIMER_CLOCK (133 * 1000 * 1000 / 16) -#define COUNT_TO_USEC(x) ((x) * 16 / 133) +#define COUNT_TO_USEC(x) ((x) / 133 * 16) #define USEC_TO_COUNT(x) ((x) * 133 / 16) #define TICKS_PER_HZ (TIMER_CLOCK / CONFIG_SYS_HZ) #define TICKS_TO_HZ(x) ((x) / TICKS_PER_HZ)
If we attempt to take a 32bit timer value and multiply it by a significant number, the core will not be able to handle it. This gives the illusion that the timer is rolling over, when in fact this is not the case. If we ensure the division in this instance is carried out before the multiplication, the issue vanishes. Signed-off-by: Lee Jones <lee.jones@linaro.org> --- arch/arm/cpu/armv7/u8500/timer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)