Message ID | 20180315203050.19791-36-andre.przywara@linaro.org |
---|---|
State | Superseded |
Headers | show
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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id w125sm3217102wmw.20.2018.03.15.13.31.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 15 Mar 2018 13:31:44 -0700 (PDT) From: Andre Przywara <andre.przywara@linaro.org> To: Stefano Stabellini <sstabellini@kernel.org>, Julien Grall <julien.grall@arm.com> Date: Thu, 15 Mar 2018 20:30:40 +0000 Message-Id: <20180315203050.19791-36-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180315203050.19791-1-andre.przywara@linaro.org> References: <20180315203050.19791-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH v2 35/45] ARM: new VGIC: Handle virtual IRQ allocation/reservation X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion <xen-devel.lists.xenproject.org> List-Unsubscribe: <https://lists.xenproject.org/mailman/options/xen-devel>, <mailto:xen-devel-request@lists.xenproject.org?subject=unsubscribe> List-Post: <mailto:xen-devel@lists.xenproject.org> List-Help: <mailto:xen-devel-request@lists.xenproject.org?subject=help> List-Subscribe: <https://lists.xenproject.org/mailman/listinfo/xen-devel>, <mailto:xen-devel-request@lists.xenproject.org?subject=subscribe> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" <xen-devel-bounces@lists.xenproject.org> |
Series |
New VGIC(-v2) implementation
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expand
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diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c index 277cf4a03e..d7ef6e32fc 100644 --- a/xen/arch/arm/vgic/vgic.c +++ b/xen/arch/arm/vgic/vgic.c @@ -712,6 +712,50 @@ bool vgic_evtchn_irq_pending(struct vcpu *v) return pending; } +bool vgic_reserve_virq(struct domain *d, unsigned int virq) +{ + if ( virq >= vgic_num_irqs(d) ) + return false; + + return !test_and_set_bit(virq, d->arch.vgic.allocated_irqs); +} + +int vgic_allocate_virq(struct domain *d, bool spi) +{ + int first, end; + unsigned int virq; + + if ( !spi ) + { + /* We only allocate PPIs. SGIs are all reserved */ + first = 16; + end = 32; + } + else + { + first = 32; + end = vgic_num_irqs(d); + } + + /* + * There is no spinlock to protect allocated_irqs, therefore + * test_and_set_bit may fail. If so retry it. + */ + do + { + virq = find_next_zero_bit(d->arch.vgic.allocated_irqs, end, first); + if ( virq >= end ) + return -1; + } while ( test_and_set_bit(virq, d->arch.vgic.allocated_irqs) ); + + return virq; +} + +void vgic_free_virq(struct domain *d, unsigned int virq) +{ + clear_bit(virq, d->arch.vgic.allocated_irqs); +} + struct irq_desc *vgic_get_hw_irq_desc(struct domain *d, struct vcpu *v, unsigned int virq) {