diff mbox series

clk: uniphier: add ethernet clock control support

Message ID 1524013533-1719-1-git-send-email-hayashi.kunihiko@socionext.com
State Accepted
Commit 461766cb69e3d4493fb1f66359a9cd667fc4c3ef
Headers show
Series clk: uniphier: add ethernet clock control support | expand

Commit Message

Kunihiko Hayashi April 18, 2018, 1:05 a.m. UTC 
Add clock control for ethernet controller on each SoC.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
 drivers/clk/uniphier/clk-uniphier-sys.c | 6 ++++++
 1 file changed, 6 insertions(+)

Comments

Masahiro Yamada April 18, 2018, 2:57 p.m. UTC | #1 
2018-04-18 10:05 GMT+09:00 Kunihiko Hayashi <hayashi.kunihiko@socionext.com>:
> Add clock control for ethernet controller on each SoC.
>
> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
> ---
>  drivers/clk/uniphier/clk-uniphier-sys.c | 6 ++++++
>  1 file changed, 6 insertions(+)

Applied to u-boot-uniphier.  Thanks!
diff mbox series

Patch

diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c b/drivers/clk/uniphier/clk-uniphier-sys.c
index c852c78..0230a18 100644
--- a/drivers/clk/uniphier/clk-uniphier-sys.c
+++ b/drivers/clk/uniphier/clk-uniphier-sys.c
@@ -21,7 +21,10 @@  const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = {
     defined(CONFIG_ARCH_UNIPHIER_PRO4) || defined(CONFIG_ARCH_UNIPHIER_PRO5) ||\
     defined(CONFIG_ARCH_UNIPHIER_PXS2) || defined(CONFIG_ARCH_UNIPHIER_LD6B)
 	UNIPHIER_LD4_SYS_CLK_NAND(2),
+	UNIPHIER_CLK_GATE_SIMPLE(6, 0x2104, 12),	/* ether (Pro4, PXs2) */
+	UNIPHIER_CLK_GATE_SIMPLE(7, 0x2104, 5),		/* ether-gb (Pro4) */
 	UNIPHIER_CLK_GATE_SIMPLE(8, 0x2104, 10),	/* stdmac */
+	UNIPHIER_CLK_GATE_SIMPLE(10, 0x2260, 0),	/* ether-phy (Pro4) */
 	UNIPHIER_CLK_GATE_SIMPLE(12, 0x2104, 6),	/* gio (Pro4, Pro5) */
 	UNIPHIER_CLK_GATE_SIMPLE(14, 0x2104, 16),	/* usb30 (Pro4, Pro5, PXs2) */
 	UNIPHIER_CLK_GATE_SIMPLE(15, 0x2104, 17),	/* usb31 (Pro4, Pro5, PXs2) */
@@ -34,6 +37,7 @@  const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = {
 const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = {
 #if defined(CONFIG_ARCH_UNIPHIER_LD11) || defined(CONFIG_ARCH_UNIPHIER_LD20)
 	UNIPHIER_LD11_SYS_CLK_NAND(2),
+	UNIPHIER_CLK_GATE_SIMPLE(6, 0x210c, 6),		/* ether */
 	UNIPHIER_CLK_GATE_SIMPLE(8, 0x210c, 8),		/* stdmac */
 	UNIPHIER_CLK_GATE_SIMPLE(14, 0x210c, 14),	/* usb30 (LD20) */
 	UNIPHIER_CLK_GATE_SIMPLE(16, 0x210c, 12),	/* usb30-phy0 (LD20) */
@@ -45,6 +49,8 @@  const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = {
 const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[] = {
 #if defined(CONFIG_ARCH_UNIPHIER_PXS3)
 	UNIPHIER_LD11_SYS_CLK_NAND(2),
+	UNIPHIER_CLK_GATE_SIMPLE(6, 0x210c, 9),		/* ether0 */
+	UNIPHIER_CLK_GATE_SIMPLE(7, 0x210c, 10),	/* ether1 */
 	UNIPHIER_CLK_GATE_SIMPLE(12, 0x210c, 4),	/* usb30 (gio0) */
 	UNIPHIER_CLK_GATE_SIMPLE(13, 0x210c, 5),	/* usb31-0 (gio1) */
 	UNIPHIER_CLK_GATE_SIMPLE(14, 0x210c, 6),	/* usb31-1 (gio1-1) */