| Message ID | 20180502221552.3873-6-richard.henderson@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | target/arm: Fixups for ARM_FEATURE_V8_FP16 | expand |
On 2 May 2018 at 23:15, Richard Henderson <richard.henderson@linaro.org> wrote: > Adding the fp16 moves to/from general registers. > > Cc: qemu-stable@nongnu.org > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > target/arm/translate-a64.c | 22 +++++++++++++++++++++- > 1 file changed, 21 insertions(+), 1 deletion(-) > > diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c > index c64c3ed99d..247a4f0cce 100644 > --- a/target/arm/translate-a64.c > +++ b/target/arm/translate-a64.c > @@ -5463,6 +5463,15 @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof) > tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_hi_offset(s, rd)); > clear_vec_high(s, true, rd); > break; > + case 3: > + /* 16 bit */ > + tmp = tcg_temp_new_i64(); > + tcg_gen_ext16u_i64(tmp, tcg_rn); > + write_fp_dreg(s, rd, tmp); > + tcg_temp_free_i64(tmp); > + break; > + default: > + g_assert_not_reached(); > } > } else { > TCGv_i64 tcg_rd = cpu_reg(s, rd); > @@ -5480,6 +5489,12 @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof) > /* 64 bits from top half */ > tcg_gen_ld_i64(tcg_rd, cpu_env, fp_reg_hi_offset(s, rn)); > break; > + case 3: > + /* 16 bit */ > + tcg_gen_ld16u_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_16)); > + break; > + default: > + g_assert_not_reached(); > } > } > } > @@ -5519,10 +5534,15 @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn) > case 0xa: /* 64 bit */ > case 0xd: /* 64 bit to top half of quad */ > break; > + case 0x6: /* 16-bit */ > + if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { > + break; > + } > + /* fallthru */ This is a switch on (sf << 3 | type << 1 | rmode), so this catches the halfprec <-> 32 bit cases, but it misses the halfprec <-> 64 bit ops, which have sf == 1. So I think you need a 'case 0xe' as well. > default: > /* all other sf/type/rmode combinations are invalid */ > unallocated_encoding(s); > - break; > + return; This is a distinct bugfix, I think (though the only effect would be generation of unnecessary dead code after the undef). > } > > if (!fp_access_check(s)) { > -- > 2.14.3 thanks -- PMM
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index c64c3ed99d..247a4f0cce 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -5463,6 +5463,15 @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof) tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_hi_offset(s, rd)); clear_vec_high(s, true, rd); break; + case 3: + /* 16 bit */ + tmp = tcg_temp_new_i64(); + tcg_gen_ext16u_i64(tmp, tcg_rn); + write_fp_dreg(s, rd, tmp); + tcg_temp_free_i64(tmp); + break; + default: + g_assert_not_reached(); } } else { TCGv_i64 tcg_rd = cpu_reg(s, rd); @@ -5480,6 +5489,12 @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof) /* 64 bits from top half */ tcg_gen_ld_i64(tcg_rd, cpu_env, fp_reg_hi_offset(s, rn)); break; + case 3: + /* 16 bit */ + tcg_gen_ld16u_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_16)); + break; + default: + g_assert_not_reached(); } } } @@ -5519,10 +5534,15 @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn) case 0xa: /* 64 bit */ case 0xd: /* 64 bit to top half of quad */ break; + case 0x6: /* 16-bit */ + if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + break; + } + /* fallthru */ default: /* all other sf/type/rmode combinations are invalid */ unallocated_encoding(s); - break; + return; } if (!fp_access_check(s)) {
Adding the fp16 moves to/from general registers. Cc: qemu-stable@nongnu.org Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/arm/translate-a64.c | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) -- 2.14.3