diff mbox series

synquacer: Enable optional OP-TEE support

Message ID 1532004055-29999-1-git-send-email-sumit.garg@linaro.org
State New
Headers show
Series synquacer: Enable optional OP-TEE support | expand

Commit Message

Sumit Garg July 19, 2018, 12:40 p.m. UTC 
OP-TEE is optional on Developerbox controlled via GPIO (DIP SW-3-3).

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>

---
 plat/socionext/synquacer/include/platform_def.h |  1 +
 plat/socionext/synquacer/platform.mk            |  4 ++++
 plat/socionext/synquacer/sq_bl31_setup.c        | 25 +++++++++++++++++--------
 3 files changed, 22 insertions(+), 8 deletions(-)

-- 
2.7.4

Comments

Daniel Thompson July 19, 2018, 3:28 p.m. UTC | #1 
On Thu, Jul 19, 2018 at 06:10:55PM +0530, Sumit Garg wrote:
> OP-TEE is optional on Developerbox controlled via GPIO (DIP SW-3-3).

> 

> Signed-off-by: Sumit Garg <sumit.garg@linaro.org>

> ---

>  plat/socionext/synquacer/include/platform_def.h |  1 +

>  plat/socionext/synquacer/platform.mk            |  4 ++++

>  plat/socionext/synquacer/sq_bl31_setup.c        | 25 +++++++++++++++++--------

>  3 files changed, 22 insertions(+), 8 deletions(-)

> 

> diff --git a/plat/socionext/synquacer/include/platform_def.h b/plat/socionext/synquacer/include/platform_def.h

> index 3e16642..09556e2 100644

> --- a/plat/socionext/synquacer/include/platform_def.h

> +++ b/plat/socionext/synquacer/include/platform_def.h

> @@ -77,5 +77,6 @@

>  #define PLAT_SQ_GICR_BASE		0x30400000

>  

>  #define PLAT_SQ_GPIO_BASE		0x51000000

> +#define PLAT_SQ_OPTEE_GPIO_EN_MASK	0x4

>  

>  #endif /* __PLATFORM_DEF_H__ */

> diff --git a/plat/socionext/synquacer/platform.mk b/plat/socionext/synquacer/platform.mk

> index 546f84a..96427a1 100644

> --- a/plat/socionext/synquacer/platform.mk

> +++ b/plat/socionext/synquacer/platform.mk

> @@ -18,6 +18,10 @@ ERRATA_A53_855873		:= 1

>  # Libraries

>  include lib/xlat_tables_v2/xlat_tables.mk

>  

> +ifeq (${SPD},opteed)

> +TF_CFLAGS_aarch64	+=	-DBL32_BASE=0xfc000000

> +endif

> +

>  PLAT_PATH		:=	plat/socionext/synquacer

>  PLAT_INCLUDES		:=	-I$(PLAT_PATH)/include		\

>  				-I$(PLAT_PATH)/drivers/scpi	\

> diff --git a/plat/socionext/synquacer/sq_bl31_setup.c b/plat/socionext/synquacer/sq_bl31_setup.c

> index 461c8de..753de7b 100644

> --- a/plat/socionext/synquacer/sq_bl31_setup.c

> +++ b/plat/socionext/synquacer/sq_bl31_setup.c

> @@ -71,14 +71,23 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2,

>  	assert(plat_params_from_bl2 == NULL);

>  

>  #ifdef BL32_BASE

> -	/* Populate entry point information for BL32 */

> -	SET_PARAM_HEAD(&bl32_image_ep_info,

> -				PARAM_EP,

> -				VERSION_1,

> -				0);

> -	SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);

> -	bl32_image_ep_info.pc = BL32_BASE;

> -	bl32_image_ep_info.spsr = sq_get_spsr_for_bl32_entry();

> +	NOTICE("TF-A compiled with SPD=opteed\n");


Not sure if compilation status merits a NOTICE(). It does not change
at runtime so is probably not important enough..
> +

> +	if (mmio_read_32(PLAT_SQ_GPIO_BASE) & PLAT_SQ_OPTEE_GPIO_EN_MASK) {


This decision should be based on the RAM description rather than
reading the GPIO directly (otherwise it may not work correctly with
older SCP firmware).

> +		NOTICE("OP-TEE is loaded by SCP firmware\n");


s/is/has been/

> +		/* Populate entry point information for BL32 */

> +		SET_PARAM_HEAD(&bl32_image_ep_info,

> +					PARAM_EP,

> +					VERSION_1,

> +					0);

> +		SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);

> +		bl32_image_ep_info.pc = BL32_BASE;

> +		bl32_image_ep_info.spsr = sq_get_spsr_for_bl32_entry();

> +	} else {

> +		NOTICE("OP-TEE is not loaded by SCP firmware\n");


s/is/has been/

> +	}

> +#else

> +	NOTICE("TF-A compiled without SPD=opteed\n");

>  #endif /* BL32_BASE */

>  

>  	/* Populate entry point information for BL33 */

> -- 

> 2.7.4

>
Sumit Garg July 20, 2018, 4:29 a.m. UTC | #2 
On Thu, 19 Jul 2018 at 20:58, Daniel Thompson
<daniel.thompson@linaro.org> wrote:
>

> On Thu, Jul 19, 2018 at 06:10:55PM +0530, Sumit Garg wrote:

> > OP-TEE is optional on Developerbox controlled via GPIO (DIP SW-3-3).

> >

> > Signed-off-by: Sumit Garg <sumit.garg@linaro.org>

> > ---

> >  plat/socionext/synquacer/include/platform_def.h |  1 +

> >  plat/socionext/synquacer/platform.mk            |  4 ++++

> >  plat/socionext/synquacer/sq_bl31_setup.c        | 25 +++++++++++++++++--------

> >  3 files changed, 22 insertions(+), 8 deletions(-)

> >

> > diff --git a/plat/socionext/synquacer/include/platform_def.h b/plat/socionext/synquacer/include/platform_def.h

> > index 3e16642..09556e2 100644

> > --- a/plat/socionext/synquacer/include/platform_def.h

> > +++ b/plat/socionext/synquacer/include/platform_def.h

> > @@ -77,5 +77,6 @@

> >  #define PLAT_SQ_GICR_BASE            0x30400000

> >

> >  #define PLAT_SQ_GPIO_BASE            0x51000000

> > +#define PLAT_SQ_OPTEE_GPIO_EN_MASK   0x4

> >

> >  #endif /* __PLATFORM_DEF_H__ */

> > diff --git a/plat/socionext/synquacer/platform.mk b/plat/socionext/synquacer/platform.mk

> > index 546f84a..96427a1 100644

> > --- a/plat/socionext/synquacer/platform.mk

> > +++ b/plat/socionext/synquacer/platform.mk

> > @@ -18,6 +18,10 @@ ERRATA_A53_855873          := 1

> >  # Libraries

> >  include lib/xlat_tables_v2/xlat_tables.mk

> >

> > +ifeq (${SPD},opteed)

> > +TF_CFLAGS_aarch64    +=      -DBL32_BASE=0xfc000000

> > +endif

> > +

> >  PLAT_PATH            :=      plat/socionext/synquacer

> >  PLAT_INCLUDES                :=      -I$(PLAT_PATH)/include          \

> >                               -I$(PLAT_PATH)/drivers/scpi     \

> > diff --git a/plat/socionext/synquacer/sq_bl31_setup.c b/plat/socionext/synquacer/sq_bl31_setup.c

> > index 461c8de..753de7b 100644

> > --- a/plat/socionext/synquacer/sq_bl31_setup.c

> > +++ b/plat/socionext/synquacer/sq_bl31_setup.c

> > @@ -71,14 +71,23 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2,

> >       assert(plat_params_from_bl2 == NULL);

> >

> >  #ifdef BL32_BASE

> > -     /* Populate entry point information for BL32 */

> > -     SET_PARAM_HEAD(&bl32_image_ep_info,

> > -                             PARAM_EP,

> > -                             VERSION_1,

> > -                             0);

> > -     SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);

> > -     bl32_image_ep_info.pc = BL32_BASE;

> > -     bl32_image_ep_info.spsr = sq_get_spsr_for_bl32_entry();

> > +     NOTICE("TF-A compiled with SPD=opteed\n");

>

> Not sure if compilation status merits a NOTICE(). It does not change

> at runtime so is probably not important enough..


Ok will remove this print.

> > +

> > +     if (mmio_read_32(PLAT_SQ_GPIO_BASE) & PLAT_SQ_OPTEE_GPIO_EN_MASK) {

>

> This decision should be based on the RAM description rather than

> reading the GPIO directly (otherwise it may not work correctly with

> older SCP firmware).


Agree, will use DRAM1 data to determine whether OP-TEE is loaded or
not. I think following check should be sufficient:

if ((dram1_base + dram1_size) <= BL32_BASE)

>

> > +             NOTICE("OP-TEE is loaded by SCP firmware\n");

>

> s/is/has been/

>


ok.

> > +             /* Populate entry point information for BL32 */

> > +             SET_PARAM_HEAD(&bl32_image_ep_info,

> > +                                     PARAM_EP,

> > +                                     VERSION_1,

> > +                                     0);

> > +             SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);

> > +             bl32_image_ep_info.pc = BL32_BASE;

> > +             bl32_image_ep_info.spsr = sq_get_spsr_for_bl32_entry();

> > +     } else {

> > +             NOTICE("OP-TEE is not loaded by SCP firmware\n");

>

> s/is/has been/

>


ok.

> > +     }

> > +#else

> > +     NOTICE("TF-A compiled without SPD=opteed\n");

> >  #endif /* BL32_BASE */

> >

> >       /* Populate entry point information for BL33 */

> > --

> > 2.7.4

> >
diff mbox series

Patch

diff --git a/plat/socionext/synquacer/include/platform_def.h b/plat/socionext/synquacer/include/platform_def.h
index 3e16642..09556e2 100644
--- a/plat/socionext/synquacer/include/platform_def.h
+++ b/plat/socionext/synquacer/include/platform_def.h
@@ -77,5 +77,6 @@ 
 #define PLAT_SQ_GICR_BASE		0x30400000
 
 #define PLAT_SQ_GPIO_BASE		0x51000000
+#define PLAT_SQ_OPTEE_GPIO_EN_MASK	0x4
 
 #endif /* __PLATFORM_DEF_H__ */
diff --git a/plat/socionext/synquacer/platform.mk b/plat/socionext/synquacer/platform.mk
index 546f84a..96427a1 100644
--- a/plat/socionext/synquacer/platform.mk
+++ b/plat/socionext/synquacer/platform.mk
@@ -18,6 +18,10 @@  ERRATA_A53_855873		:= 1
 # Libraries
 include lib/xlat_tables_v2/xlat_tables.mk
 
+ifeq (${SPD},opteed)
+TF_CFLAGS_aarch64	+=	-DBL32_BASE=0xfc000000
+endif
+
 PLAT_PATH		:=	plat/socionext/synquacer
 PLAT_INCLUDES		:=	-I$(PLAT_PATH)/include		\
 				-I$(PLAT_PATH)/drivers/scpi	\
diff --git a/plat/socionext/synquacer/sq_bl31_setup.c b/plat/socionext/synquacer/sq_bl31_setup.c
index 461c8de..753de7b 100644
--- a/plat/socionext/synquacer/sq_bl31_setup.c
+++ b/plat/socionext/synquacer/sq_bl31_setup.c
@@ -71,14 +71,23 @@  void bl31_early_platform_setup(bl31_params_t *from_bl2,
 	assert(plat_params_from_bl2 == NULL);
 
 #ifdef BL32_BASE
-	/* Populate entry point information for BL32 */
-	SET_PARAM_HEAD(&bl32_image_ep_info,
-				PARAM_EP,
-				VERSION_1,
-				0);
-	SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
-	bl32_image_ep_info.pc = BL32_BASE;
-	bl32_image_ep_info.spsr = sq_get_spsr_for_bl32_entry();
+	NOTICE("TF-A compiled with SPD=opteed\n");
+
+	if (mmio_read_32(PLAT_SQ_GPIO_BASE) & PLAT_SQ_OPTEE_GPIO_EN_MASK) {
+		NOTICE("OP-TEE is loaded by SCP firmware\n");
+		/* Populate entry point information for BL32 */
+		SET_PARAM_HEAD(&bl32_image_ep_info,
+					PARAM_EP,
+					VERSION_1,
+					0);
+		SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
+		bl32_image_ep_info.pc = BL32_BASE;
+		bl32_image_ep_info.spsr = sq_get_spsr_for_bl32_entry();
+	} else {
+		NOTICE("OP-TEE is not loaded by SCP firmware\n");
+	}
+#else
+	NOTICE("TF-A compiled without SPD=opteed\n");
 #endif /* BL32_BASE */
 
 	/* Populate entry point information for BL33 */