@@ -1,7 +1,7 @@
/** @file
*
-* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
-* Copyright (c) 2015, Linaro Limited. All rights reserved.
+* Copyright (c) 2015 - 2018, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015 - 2018, Linaro Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
@@ -32,6 +32,11 @@
#define S1_BASE 0x40000000000
+#define RASC_BASE (0x5000)
+/* configuration register for Rank statistical information */
+#define RASC_CFG_INFOIDX_REG (RASC_BASE + 0x5C)
+/* configuration register for Sparing level */
+#define RASC_CFG_SPLVL_REG (RASC_BASE + 0xB8)
//
// ACPI table information used to initialize tables.
@@ -30,6 +30,18 @@
// Max NUMA node number for each node type
#define MAX_NUM_PER_TYPE 8
+#define RASC_BASE (0x5000)
+/* configuration register for Rank statistical information */
+#define RASC_CFG_INFOIDX_REG (RASC_BASE + 0x5C)
+/* configuration register for Sparing level */
+#define RASC_CFG_SPLVL_REG (RASC_BASE + 0xB8)
+
+// for acpi
+#define NODE_IN_SOCKET 2
+#define CORE_NUM_PER_SOCKET 32
+#define EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT 10
+#define EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_COUNT 8
+
#define S1_BASE 0x40000000000
//