[PULL,09/21] cputlb: fix assert_cpu_is_self macro

Message ID	20181016174911.9052-10-richard.henderson@linaro.org
State	Superseded
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Date: Tue, 16 Oct 2018 10:48:59 -0700 Message-Id: <20181016174911.9052-10-richard.henderson@linaro.org> In-Reply-To: <20181016174911.9052-1-richard.henderson@linaro.org> References: <20181016174911.9052-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PULL 09/21] cputlb: fix assert_cpu_is_self macro Precedence: list Cc: peter.maydell@linaro.org, "Emilio G. Cota" <cota@braap.org> Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org>
Series	tcg patch queue \| expand [PULL,00/21] tcg patch queue [PULL,01/21] tcg: Implement CPU_LOG_TB_NOCHAIN during expansion [PULL,02/21] tcg: access cpu->icount_decr.u16.high with atomics [PULL,03/21] tcg: fix use of uninitialized variable under CONFIG_PROFILER [PULL,04/21] tcg: plug holes in struct TCGProfile [PULL,05/21] tcg: distribute tcg_time into TCG contexts [PULL,06/21] target/alpha: remove tlb_flush from alpha_cpu_initfn [PULL,07/21] target/unicore32: remove tlb_flush from uc32_init_fn [PULL,08/21] exec: introduce tlb_init [PULL,09/21] cputlb: fix assert_cpu_is_self macro [PULL,10/21] cputlb: serialize tlb updates with env->tlb_lock [PULL,11/21] tcg: Add tlb_index and tlb_entry helpers [PULL,12/21] tcg: Split CONFIG_ATOMIC128 [PULL,13/21] target/i386: Convert to HAVE_CMPXCHG128 [PULL,14/21] target/arm: Convert to HAVE_CMPXCHG128 [PULL,15/21] target/arm: Check HAVE_CMPXCHG128 at translate time [PULL,16/21] target/ppc: Convert to HAVE_CMPXCHG128 and HAVE_ATOMIC128 [PULL,17/21] target/s390x: Convert to HAVE_CMPXCHG128 and HAVE_ATOMIC128 [PULL,18/21] target/s390x: Split do_cdsg, do_lpq, do_stpq [PULL,19/21] target/s390x: Skip wout, cout helpers if op helper does not return [PULL,20/21] target/s390x: Check HAVE_ATOMIC128 and HAVE_CMPXCHG128 at translate [PULL,21/21] cputlb: read CPUTLBEntry.addr_write atomically

Message ID

20181016174911.9052-10-richard.henderson@linaro.org

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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Date: Tue, 16 Oct 2018 10:48:59 -0700
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Subject: [Qemu-devel] [PULL 09/21] cputlb: fix assert_cpu_is_self macro
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Cc: peter.maydell@linaro.org, "Emilio G. Cota" <cota@braap.org>
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Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org>

Series

tcg patch queue | expand

Commit Message

Richard Henderson Oct. 16, 2018, 5:48 p.m. UTC

From: "Emilio G. Cota" <cota@braap.org>


Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

Signed-off-by: Emilio G. Cota <cota@braap.org>

Message-Id: <20181009174557.16125-5-cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 accel/tcg/cputlb.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

-- 
2.17.2

diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 502eea2850..f6b388c961 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -58,9 +58,9 @@ 
     } \
 } while (0)
 
-#define assert_cpu_is_self(this_cpu) do {                         \
+#define assert_cpu_is_self(cpu) do {                              \
         if (DEBUG_TLB_GATE) {                                     \
-            g_assert(!cpu->created || qemu_cpu_is_self(cpu));     \
+            g_assert(!(cpu)->created || qemu_cpu_is_self(cpu));   \
         }                                                         \
     } while (0)

[PULL,09/21] cputlb: fix assert_cpu_is_self macro

Commit Message

Patch