| Message ID | 20190501043734.26706-4-bjorn.andersson@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | None | expand |
Hi, On Tue, Apr 30, 2019 at 9:37 PM Bjorn Andersson <bjorn.andersson@linaro.org> wrote: > > The AOSS QMP provides a number of power domains, used for QDSS and > PIL, add the node for this. > > Tested-by: Sibi Sankar <sibis@codeaurora.org> > Reviewed-by: Sibi Sankar <sibis@codeaurora.org> > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> > --- > > Changes since v6: > - Added #clock-cells > > arch/arm64/boot/dts/qcom/sdm845.dtsi | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi > index fcb93300ca62..666bc88d3e81 100644 > --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi > +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi > @@ -14,6 +14,7 @@ > #include <dt-bindings/interconnect/qcom,sdm845.h> > #include <dt-bindings/interrupt-controller/arm-gic.h> > #include <dt-bindings/phy/phy-qcom-qusb2.h> > +#include <dt-bindings/power/qcom-aoss-qmp.h> > #include <dt-bindings/power/qcom-rpmpd.h> > #include <dt-bindings/reset/qcom,sdm845-aoss.h> > #include <dt-bindings/reset/qcom,sdm845-pdc.h> > @@ -2142,6 +2143,15 @@ Please avoid editing patches by hand. I needed to manually change the "15" above to "16" to apply. -Doug
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index fcb93300ca62..666bc88d3e81 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -14,6 +14,7 @@ #include <dt-bindings/interconnect/qcom,sdm845.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/phy/phy-qcom-qusb2.h> +#include <dt-bindings/power/qcom-aoss-qmp.h> #include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/reset/qcom,sdm845-aoss.h> #include <dt-bindings/reset/qcom,sdm845-pdc.h> @@ -2142,6 +2143,15 @@ #reset-cells = <1>; }; + aoss_qmp: qmp@c300000 { + compatible = "qcom,sdm845-aoss-qmp"; + reg = <0 0x0c300000 0 0x100000>; + interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; + mboxes = <&apss_shared 0>; + + #clock-cells = <0>; + #power-domain-cells = <1>; + }; + spmi_bus: spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; reg = <0 0x0c440000 0 0x1100>,