| Message ID | 20190722213958.5761-9-julien.grall@arm.com |
|---|---|
| State | New |
| Headers | show |
| Series | xen/arm: Rework head.S to make it more compliant with the Arm Arm | expand |
On Mon, 22 Jul 2019, Julien Grall wrote: > On secondary CPUs, zero_bss() will be a NOP because BSS only need to be > zeroed once at boot. So the call in the secondary CPUs path can be > removed. It also means that x26 does not need to be set for secondary > CPU. > > Note that we will need to keep x26 around for the boot CPU as BSS should > not be reset when booting via UEFI. > > Lastly, document the behavior and the main registers usage within the > function. > > Signed-off-by: Julien Grall <julien.grall@arm.com> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org> > --- > Changes in v2: > - Clarify the commit message > - Mention x20 is used as an input > --- > xen/arch/arm/arm64/head.S | 14 ++++++++++---- > 1 file changed, 10 insertions(+), 4 deletions(-) > > diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S > index fbcc792ade..92c8338d71 100644 > --- a/xen/arch/arm/arm64/head.S > +++ b/xen/arch/arm/arm64/head.S > @@ -71,7 +71,7 @@ > * x23 - UART address > * x24 - > * x25 - identity map in place > - * x26 - skip_zero_bss > + * x26 - skip_zero_bss (boot cpu only) > * x27 - > * x28 - > * x29 - > @@ -313,8 +313,6 @@ GLOBAL(init_secondary) > sub x20, x19, x0 /* x20 := phys-offset */ > > mov x22, #1 /* x22 := is_secondary_cpu */ > - /* Boot CPU already zero BSS so skip it on secondary CPUs. */ > - mov x26, #1 /* X26 := skip_zero_bss */ > > mrs x0, mpidr_el1 > ldr x13, =(~MPIDR_HWID_MASK) > @@ -337,7 +335,6 @@ GLOBAL(init_secondary) > PRINT(" booting -\r\n") > #endif > bl check_cpu_mode > - bl zero_bss > bl cpu_init > bl create_page_tables > bl enable_mmu > @@ -375,6 +372,15 @@ check_cpu_mode: > b fail > ENDPROC(check_cpu_mode) > > +/* > + * Zero BSS > + * > + * Inputs: > + * x20: Physical offset > + * x26: Do we need to zero BSS? > + * > + * Clobbers x0 - x3 > + */ > zero_bss: > /* Zero BSS only when requested */ > cbnz x26, skip_bss > -- > 2.11.0 >
diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S index fbcc792ade..92c8338d71 100644 --- a/xen/arch/arm/arm64/head.S +++ b/xen/arch/arm/arm64/head.S @@ -71,7 +71,7 @@ * x23 - UART address * x24 - * x25 - identity map in place - * x26 - skip_zero_bss + * x26 - skip_zero_bss (boot cpu only) * x27 - * x28 - * x29 - @@ -313,8 +313,6 @@ GLOBAL(init_secondary) sub x20, x19, x0 /* x20 := phys-offset */ mov x22, #1 /* x22 := is_secondary_cpu */ - /* Boot CPU already zero BSS so skip it on secondary CPUs. */ - mov x26, #1 /* X26 := skip_zero_bss */ mrs x0, mpidr_el1 ldr x13, =(~MPIDR_HWID_MASK) @@ -337,7 +335,6 @@ GLOBAL(init_secondary) PRINT(" booting -\r\n") #endif bl check_cpu_mode - bl zero_bss bl cpu_init bl create_page_tables bl enable_mmu @@ -375,6 +372,15 @@ check_cpu_mode: b fail ENDPROC(check_cpu_mode) +/* + * Zero BSS + * + * Inputs: + * x20: Physical offset + * x26: Do we need to zero BSS? + * + * Clobbers x0 - x3 + */ zero_bss: /* Zero BSS only when requested */ cbnz x26, skip_bss
On secondary CPUs, zero_bss() will be a NOP because BSS only need to be zeroed once at boot. So the call in the secondary CPUs path can be removed. It also means that x26 does not need to be set for secondary CPU. Note that we will need to keep x26 around for the boot CPU as BSS should not be reset when booting via UEFI. Lastly, document the behavior and the main registers usage within the function. Signed-off-by: Julien Grall <julien.grall@arm.com> --- Changes in v2: - Clarify the commit message - Mention x20 is used as an input --- xen/arch/arm/arm64/head.S | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-)