| Message ID | 2312c9a10e7251d69e31e4f51c0f1d70e6f2f2f5.1591708204.git.saiprakash.ranjan@codeaurora.org |
|---|---|
| State | Accepted |
| Commit | 015156e689aa1f0c836f9ef4d342b6f6897afd74 |
| Headers | show |
| Series | Add coresight support for SM8150 and few changes to SC7180 | expand |
On Tue 09 Jun 06:30 PDT 2020, Sai Prakash Ranjan wrote: > Define iommus property for Coresight ETR component in > SC7180 SoC with the SID and mask to enable SMMU > translation for this master. > We don't have &apps_smmu in linux-next, as we've yet to figure out how to disable the boot splash or support the stream mapping handover. So I'm not able to apply this. Regards, Bjorn > Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> > --- > arch/arm64/boot/dts/qcom/sc7180.dtsi | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi > index f684a0b87848..9b38867740ca 100644 > --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi > @@ -1711,6 +1711,7 @@ > etr@6048000 { > compatible = "arm,coresight-tmc", "arm,primecell"; > reg = <0 0x06048000 0 0x1000>; > + iommus = <&apps_smmu 0x04a0 0x20>; > > clocks = <&aoss_qmp>; > clock-names = "apb_pclk"; > -- > QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member > of Code Aurora Forum, hosted by The Linux Foundation >
Hi Bjorn, On 2020-06-21 12:52, Bjorn Andersson wrote: > On Tue 09 Jun 06:30 PDT 2020, Sai Prakash Ranjan wrote: > >> Define iommus property for Coresight ETR component in >> SC7180 SoC with the SID and mask to enable SMMU >> translation for this master. >> > > We don't have &apps_smmu in linux-next, as we've yet to figure out how > to disable the boot splash or support the stream mapping handover. > > So I'm not able to apply this. > This is for SC7180 which has apps_smmu not SM8150. Thanks, Sai -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index f684a0b87848..9b38867740ca 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1711,6 +1711,7 @@ etr@6048000 { compatible = "arm,coresight-tmc", "arm,primecell"; reg = <0 0x06048000 0 0x1000>; + iommus = <&apps_smmu 0x04a0 0x20>; clocks = <&aoss_qmp>; clock-names = "apb_pclk";
Define iommus property for Coresight ETR component in SC7180 SoC with the SID and mask to enable SMMU translation for this master. Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 1 + 1 file changed, 1 insertion(+)