| Message ID | 1593507574-10007-2-git-send-email-hayashi.kunihiko@socionext.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add new UniPhier AHCI PHY driver | expand |
On 30-06-20, 17:59, Kunihiko Hayashi wrote: > Add DT bindings for PHY interface built into ahci controller implemented > in UniPhier SoCs. Rob ? > > Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> > --- > .../bindings/phy/socionext,uniphier-ahci-phy.yaml | 76 ++++++++++++++++++++++ > 1 file changed, 76 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/socionext,uniphier-ahci-phy.yaml > > diff --git a/Documentation/devicetree/bindings/phy/socionext,uniphier-ahci-phy.yaml b/Documentation/devicetree/bindings/phy/socionext,uniphier-ahci-phy.yaml > new file mode 100644 > index 0000000..bab2ff4 > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/socionext,uniphier-ahci-phy.yaml > @@ -0,0 +1,76 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/socionext,uniphier-ahci-phy.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Socionext UniPhier AHCI PHY > + > +description: | > + This describes the deivcetree bindings for PHY interfaces built into > + AHCI controller implemented on Socionext UniPhier SoCs. > + > +maintainers: > + - Kunihiko Hayashi <hayashi.kunihiko@socionext.com> > + > +properties: > + compatible: > + enum: > + - socionext,uniphier-pxs2-ahci-phy > + - socionext,uniphier-pxs3-ahci-phy > + > + reg: > + description: PHY register region (offset and length) > + > + "#phy-cells": > + const: 0 > + > + clocks: > + maxItems: 2 > + > + clock-names: > + oneOf: > + - items: # for PXs2 > + - const: link > + - items: # for others > + - const: link > + - const: phy > + > + resets: > + maxItems: 2 > + > + reset-names: > + items: > + - const: link > + - const: phy > + > +required: > + - compatible > + - reg > + - "#phy-cells" > + - clocks > + - clock-names > + - resets > + - reset-names > + > +additionalProperties: false > + > +examples: > + - | > + ahci-glue@65700000 { > + compatible = "socionext,uniphier-pxs3-ahci-glue", > + "simple-mfd"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0 0x65700000 0x100>; > + > + ahci_phy: phy@10 { > + compatible = "socionext,uniphier-pxs3-ahci-phy"; > + reg = <0x10 0x10>; > + #phy-cells = <0>; > + clock-names = "link", "phy"; > + clocks = <&sys_clk 28>, <&sys_clk 30>; > + reset-names = "link", "phy"; > + resets = <&sys_rst 28>, <&sys_rst 30>; > + }; > + }; > -- > 2.7.4 -- ~Vinod
On Tue, 30 Jun 2020 17:59:33 +0900, Kunihiko Hayashi wrote: > Add DT bindings for PHY interface built into ahci controller implemented > in UniPhier SoCs. > > Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> > --- > .../bindings/phy/socionext,uniphier-ahci-phy.yaml | 76 ++++++++++++++++++++++ > 1 file changed, 76 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/socionext,uniphier-ahci-phy.yaml > Reviewed-by: Rob Herring <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/phy/socionext,uniphier-ahci-phy.yaml b/Documentation/devicetree/bindings/phy/socionext,uniphier-ahci-phy.yaml new file mode 100644 index 0000000..bab2ff4 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/socionext,uniphier-ahci-phy.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/socionext,uniphier-ahci-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Socionext UniPhier AHCI PHY + +description: | + This describes the deivcetree bindings for PHY interfaces built into + AHCI controller implemented on Socionext UniPhier SoCs. + +maintainers: + - Kunihiko Hayashi <hayashi.kunihiko@socionext.com> + +properties: + compatible: + enum: + - socionext,uniphier-pxs2-ahci-phy + - socionext,uniphier-pxs3-ahci-phy + + reg: + description: PHY register region (offset and length) + + "#phy-cells": + const: 0 + + clocks: + maxItems: 2 + + clock-names: + oneOf: + - items: # for PXs2 + - const: link + - items: # for others + - const: link + - const: phy + + resets: + maxItems: 2 + + reset-names: + items: + - const: link + - const: phy + +required: + - compatible + - reg + - "#phy-cells" + - clocks + - clock-names + - resets + - reset-names + +additionalProperties: false + +examples: + - | + ahci-glue@65700000 { + compatible = "socionext,uniphier-pxs3-ahci-glue", + "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x65700000 0x100>; + + ahci_phy: phy@10 { + compatible = "socionext,uniphier-pxs3-ahci-phy"; + reg = <0x10 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 28>, <&sys_clk 30>; + reset-names = "link", "phy"; + resets = <&sys_rst 28>, <&sys_rst 30>; + }; + };
Add DT bindings for PHY interface built into ahci controller implemented in UniPhier SoCs. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> --- .../bindings/phy/socionext,uniphier-ahci-phy.yaml | 76 ++++++++++++++++++++++ 1 file changed, 76 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/socionext,uniphier-ahci-phy.yaml -- 2.7.4