@@ -26,6 +26,7 @@ properties:
- amlogic,meson8-pwrc
- amlogic,meson8b-pwrc
- amlogic,meson8m2-pwrc
+ - amlogic,meson-gxbb-pwrc
- amlogic,meson-g12a-pwrc
- amlogic,meson-sm1-pwrc
@@ -42,6 +43,7 @@ properties:
resets:
minItems: 11
+ maxItems: 12
"#power-domain-cells":
const: 1
@@ -77,6 +79,31 @@ allOf:
- resets
- reset-names
+ - if:
+ properties:
+ compatible:
+ enum:
+ - amlogic,meson-gxbb-pwrc
+ then:
+ properties:
+ reset-names:
+ items:
+ - const: viu
+ - const: venc
+ - const: vcbus
+ - const: bt656
+ - const: dvin
+ - const: rdma
+ - const: venci
+ - const: vencp
+ - const: vdac
+ - const: vdi6
+ - const: vencl
+ - const: vid_lock
+ required:
+ - resets
+ - reset-names
+
- if:
properties:
compatible:
new file mode 100644
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
+/*
+ * Copyright (c) 2019 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#ifndef _DT_BINDINGS_MESON_GXBB_POWER_H
+#define _DT_BINDINGS_MESON_GXBB_POWER_H
+
+#define PWRC_GXBB_VPU_ID 0
+#define PWRC_GXBB_ETH_ID 1
+
+#endif
The power domains on the GX SoCs are very similar to G12A. The only known differences so far are: - The GX SoCs do not have the HHI_VPU_MEM_PD_REG2 register (for the VPU power-domain) - The GX SoCs have an additional reset line called "dvin" Add a new compatible string and adjust the reset line expectations for these SoCs. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> --- .../bindings/power/amlogic,meson-ee-pwrc.yaml | 27 +++++++++++++++++++ include/dt-bindings/power/meson-gxbb-power.h | 13 +++++++++ 2 files changed, 40 insertions(+) create mode 100644 include/dt-bindings/power/meson-gxbb-power.h