@@ -44,6 +44,7 @@
#define PWDN_ACTIVE_DELAY_MS 20
#define MIPI_CTRL00_CLOCK_LANE_GATE BIT(5)
+#define MIPI_CTRL00_LINE_SYNC_ENABLE BIT(4)
#define MIPI_CTRL00_BUS_IDLE BIT(2)
#define MIPI_CTRL00_CLOCK_LANE_DISABLE BIT(0)
@@ -95,6 +96,7 @@ struct ov5647 {
int power_count;
struct clk *xclk;
struct gpio_desc *pwdn;
+ bool is_clock_contiguous;
};
static inline struct ov5647 *to_state(struct v4l2_subdev *sd)
@@ -274,9 +276,15 @@ static int ov5647_set_virtual_channel(struct v4l2_subdev *sd, int channel)
static int ov5647_stream_on(struct v4l2_subdev *sd)
{
+ struct ov5647 *ov5647 = to_state(sd);
+ u8 val = MIPI_CTRL00_BUS_IDLE;
int ret;
- ret = ov5647_write(sd, OV5647_REG_MIPI_CTRL00, MIPI_CTRL00_BUS_IDLE);
+ if (ov5647->is_clock_contiguous)
+ val |= MIPI_CTRL00_CLOCK_LANE_GATE |
+ MIPI_CTRL00_LINE_SYNC_ENABLE;
+
+ ret = ov5647_write(sd, OV5647_REG_MIPI_CTRL00, val);
if (ret < 0)
return ret;
@@ -573,7 +581,7 @@ static const struct v4l2_subdev_internal_ops ov5647_subdev_internal_ops = {
.open = ov5647_open,
};
-static int ov5647_parse_dt(struct device_node *np)
+static int ov5647_parse_dt(struct ov5647 *sensor, struct device_node *np)
{
struct v4l2_fwnode_endpoint bus_cfg = { .bus_type = 0 };
struct device_node *ep;
@@ -586,6 +594,17 @@ static int ov5647_parse_dt(struct device_node *np)
ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(ep), &bus_cfg);
+ if (!ret) {
+ of_node_put(ep);
+ of_node_put(np);
+ return ret;
+ }
+
+ if (bus_cfg.bus_type == V4L2_MBUS_CSI2_DPHY
+ || bus_cfg.bus_type == V4L2_MBUS_CSI2_CPHY)
+ sensor->is_clock_contiguous = bus_cfg.bus.mipi_csi2.flags
+ & V4L2_MBUS_CSI2_NONCONTINUOUS_CLOCK;
+
of_node_put(ep);
return ret;
}
@@ -604,7 +623,7 @@ static int ov5647_probe(struct i2c_client *client)
return -ENOMEM;
if (IS_ENABLED(CONFIG_OF) && np) {
- ret = ov5647_parse_dt(np);
+ ret = ov5647_parse_dt(sensor, np);
if (ret) {
dev_err(dev, "DT parsing error: %d\n", ret);
return ret;