@@ -216,6 +216,29 @@ mmu_ipu: mmu@0 {
};
};
+ dsp: dsp {
+ compatible = "ti,omap5-dsp";
+ ti,bootreg = <&scm_conf 0x304 0>;
+ iommus = <&mmu_dsp>;
+ resets = <&prm_dsp 0>;
+ clocks = <&dsp_clkctrl OMAP5_MMU_DSP_CLKCTRL 0>;
+ firmware-name = "omap5-dsp-fw.xe64T";
+ mboxes = <&mailbox &mbox_dsp>;
+ status = "disabled";
+ };
+
+ ipu: ipu@55020000 {
+ compatible = "ti,omap5-ipu";
+ reg = <0x55020000 0x10000>;
+ reg-names = "l2ram";
+ iommus = <&mmu_ipu>;
+ resets = <&prm_core 0>, <&prm_core 1>;
+ clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>;
+ firmware-name = "omap5-ipu-fw.xem4";
+ mboxes = <&mailbox &mbox_ipu>;
+ status = "disabled";
+ };
+
dmm@4e000000 {
compatible = "ti,omap5-dmm";
reg = <0x4e000000 0x800>;
OMAP5, like OMAP4, also has two remote processor subsystems, DSP and IPU. The IPU subsystem though has dual Cortex-M4 processors instead of the dual Cortex-M3 processors in OMAP4, but otherwise has almost the same set of features. Add the DT nodes for these two processor sub-systems for all OMAP5 SoCs. The nodes have the 'iommus', 'clocks', 'resets', 'firmware' and 'mboxes' properties added, and are disabled for now. The IPU node has its L2 RAM memory specified through the 'reg' and 'reg-names' properties. The DSP node doesn't have these since it doesn't have any L2 RAM memories, but has an additional 'ti,bootreg' property instead as it has a specific boot register that needs to be programmed for booting. These nodes should be enabled as per the individual product configuration in the corresponding board dts files. Signed-off-by: Suman Anna <s-anna@ti.com> --- arch/arm/boot/dts/omap5.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) -- 2.26.0