| Message ID | 1578474868-36271-1-git-send-email-ley.foon.tan@intel.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v4] reset: socfpga: Poll for reset status after deassert reset | expand |
On 1/8/20 10:14 AM, Ley Foon Tan wrote: > In Cyclone 5 SoC platform, the first USB probing is failed but second > probing is success. DWC2 USB driver read gsnpsid register right after > de-assert reset, but controller is not ready yet and it returns gsnpsid 0. > Polling reset status after de-assert reset to solve the issue. > > Retry with this fix more than 10 times without issue. > > Signed-off-by: Ley Foon Tan <ley.foon.tan at intel.com> > > --- > v4: > - Change to use get_timer() for timeout. > > v3: > - Remove _status callback and poll reset status after deassert reset > - https://patchwork.ozlabs.org/patch/1218026/ > > v2: > - https://patchwork.ozlabs.org/cover/1215174/ > > v1: > - https://patchwork.ozlabs.org/patch/1214841/ > --- > drivers/reset/reset-socfpga.c | 14 +++++++++++++- > 1 file changed, 13 insertions(+), 1 deletion(-) > > diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c > index 93ec9cfdb6..a08967b648 100644 > --- a/drivers/reset/reset-socfpga.c > +++ b/drivers/reset/reset-socfpga.c > @@ -78,9 +78,21 @@ static int socfpga_reset_deassert(struct reset_ctl *reset_ctl) > int reg_width = sizeof(u32); > int bank = id / (reg_width * BITS_PER_BYTE); > int offset = id % (reg_width * BITS_PER_BYTE); > + ulong start; > + u32 status; > > clrbits_le32(data->modrst_base + (bank * BANK_INCREMENT), BIT(offset)); > - return 0; > + > + /* Poll until reset is completed. */ > + start = get_timer(0); > + do { > + status = readl(data->modrst_base + (bank * BANK_INCREMENT)) & > + BIT(offset); > + if (!status) > + return 0; > + } while (get_timer(start) < 200); > + > + return -ETIMEDOUT; Isn't this like open-coded wait_for_bit...() ?
> -----Original Message----- > From: Marek Vasut <marex at denx.de> > Sent: Thursday, January 9, 2020 10:44 PM > To: Tan, Ley Foon <ley.foon.tan at intel.com>; u-boot at lists.denx.de > Cc: Simon Goldschmidt <simon.k.r.goldschmidt at gmail.com>; Simon Glass > <sjg at chromium.org>; Joe Hershberger <joe.hershberger at ni.com>; Ley > Foon Tan <lftan.linux at gmail.com>; See, Chin Liang > <chin.liang.see at intel.com>; Chee, Tien Fong <tien.fong.chee at intel.com> > Subject: Re: [PATCH v4] reset: socfpga: Poll for reset status after deassert > reset > > On 1/8/20 10:14 AM, Ley Foon Tan wrote: > > In Cyclone 5 SoC platform, the first USB probing is failed but second > > probing is success. DWC2 USB driver read gsnpsid register right after > > de-assert reset, but controller is not ready yet and it returns gsnpsid 0. > > Polling reset status after de-assert reset to solve the issue. > > > > Retry with this fix more than 10 times without issue. > > > > Signed-off-by: Ley Foon Tan <ley.foon.tan at intel.com> > > > > --- > > v4: > > - Change to use get_timer() for timeout. > > > > v3: > > - Remove _status callback and poll reset status after deassert reset > > - https://patchwork.ozlabs.org/patch/1218026/ > > > > v2: > > - https://patchwork.ozlabs.org/cover/1215174/ > > > > v1: > > - https://patchwork.ozlabs.org/patch/1214841/ > > --- > > drivers/reset/reset-socfpga.c | 14 +++++++++++++- > > 1 file changed, 13 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/reset/reset-socfpga.c > > b/drivers/reset/reset-socfpga.c index 93ec9cfdb6..a08967b648 100644 > > --- a/drivers/reset/reset-socfpga.c > > +++ b/drivers/reset/reset-socfpga.c > > @@ -78,9 +78,21 @@ static int socfpga_reset_deassert(struct reset_ctl > *reset_ctl) > > int reg_width = sizeof(u32); > > int bank = id / (reg_width * BITS_PER_BYTE); > > int offset = id % (reg_width * BITS_PER_BYTE); > > + ulong start; > > + u32 status; > > > > clrbits_le32(data->modrst_base + (bank * BANK_INCREMENT), > BIT(offset)); > > - return 0; > > + > > + /* Poll until reset is completed. */ > > + start = get_timer(0); > > + do { > > + status = readl(data->modrst_base + (bank * > BANK_INCREMENT)) & > > + BIT(offset); > > + if (!status) > > + return 0; > > + } while (get_timer(start) < 200); > > + > > + return -ETIMEDOUT; > > Isn't this like open-coded wait_for_bit...() ? Yes, you are right. Will change to it. Thanks. Regards Ley Foon
diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c index 93ec9cfdb6..a08967b648 100644 --- a/drivers/reset/reset-socfpga.c +++ b/drivers/reset/reset-socfpga.c @@ -78,9 +78,21 @@ static int socfpga_reset_deassert(struct reset_ctl *reset_ctl) int reg_width = sizeof(u32); int bank = id / (reg_width * BITS_PER_BYTE); int offset = id % (reg_width * BITS_PER_BYTE); + ulong start; + u32 status; clrbits_le32(data->modrst_base + (bank * BANK_INCREMENT), BIT(offset)); - return 0; + + /* Poll until reset is completed. */ + start = get_timer(0); + do { + status = readl(data->modrst_base + (bank * BANK_INCREMENT)) & + BIT(offset); + if (!status) + return 0; + } while (get_timer(start) < 200); + + return -ETIMEDOUT; } static int socfpga_reset_request(struct reset_ctl *reset_ctl)
In Cyclone 5 SoC platform, the first USB probing is failed but second probing is success. DWC2 USB driver read gsnpsid register right after de-assert reset, but controller is not ready yet and it returns gsnpsid 0. Polling reset status after de-assert reset to solve the issue. Retry with this fix more than 10 times without issue. Signed-off-by: Ley Foon Tan <ley.foon.tan at intel.com> --- v4: - Change to use get_timer() for timeout. v3: - Remove _status callback and poll reset status after deassert reset - https://patchwork.ozlabs.org/patch/1218026/ v2: - https://patchwork.ozlabs.org/cover/1215174/ v1: - https://patchwork.ozlabs.org/patch/1214841/ --- drivers/reset/reset-socfpga.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-)