diff mbox series

[PATCHv2,08/10] pci: layerscaple: Modify the ls_pcie_dump_atu function

Message ID 20200709153142.3644-9-Zhiqiang.Hou@nxp.com
State New
Headers show
Series pci: layerscape: Split EP mode code into a | expand

Commit Message

Zhiqiang Hou July 9, 2020, 3:31 p.m. UTC 
From: Xiaowei Bao <xiaowei.bao at nxp.com>

Modify the ls_pcie_dump_atu function, make it can print the INBOUND
windows registers.

Signed-off-by: Xiaowei Bao <xiaowei.bao at nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou at nxp.com>
---
V2:
 - Rebase the patch without change intent.

 drivers/pci/pcie_layerscape.c    | 25 +++++++++++++------------
 drivers/pci/pcie_layerscape.h    |  2 +-
 drivers/pci/pcie_layerscape_ep.c |  3 +++
 drivers/pci/pcie_layerscape_rc.c |  2 +-
 4 files changed, 18 insertions(+), 14 deletions(-)
diff mbox series

Patch

diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index 0116af8aa5..25b5272d4e 100644
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -121,24 +121,25 @@  void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, u32 pf, u32 vf_flag,
 		   PCIE_ATU_BAR_NUM(bar), PCIE_ATU_CR2);
 }
 
-void ls_pcie_dump_atu(struct ls_pcie *pcie)
+void ls_pcie_dump_atu(struct ls_pcie *pcie, u32 win_num, u32 type)
 {
-	int i;
+	int win_idx;
 
-	for (i = 0; i < PCIE_ATU_REGION_NUM; i++) {
-		dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | i,
-			   PCIE_ATU_VIEWPORT);
-		debug("iATU%d:\n", i);
+	for (win_idx = 0; win_idx < win_num; win_idx++) {
+		dbi_writel(pcie, type | win_idx, PCIE_ATU_VIEWPORT);
+		debug("iATU%d:\n", win_idx);
 		debug("\tLOWER PHYS 0x%08x\n",
 		      dbi_readl(pcie, PCIE_ATU_LOWER_BASE));
 		debug("\tUPPER PHYS 0x%08x\n",
 		      dbi_readl(pcie, PCIE_ATU_UPPER_BASE));
-		debug("\tLOWER BUS  0x%08x\n",
-		      dbi_readl(pcie, PCIE_ATU_LOWER_TARGET));
-		debug("\tUPPER BUS  0x%08x\n",
-		      dbi_readl(pcie, PCIE_ATU_UPPER_TARGET));
-		debug("\tLIMIT      0x%08x\n",
-		      dbi_readl(pcie, PCIE_ATU_LIMIT));
+		if (type == PCIE_ATU_REGION_OUTBOUND) {
+			debug("\tLOWER BUS  0x%08x\n",
+			      dbi_readl(pcie, PCIE_ATU_LOWER_TARGET));
+			debug("\tUPPER BUS  0x%08x\n",
+			      dbi_readl(pcie, PCIE_ATU_UPPER_TARGET));
+			debug("\tLIMIT      0x%08x\n",
+			      dbi_readl(pcie, PCIE_ATU_LIMIT));
+		}
 		debug("\tCR1        0x%08x\n",
 		      dbi_readl(pcie, PCIE_ATU_CR1));
 		debug("\tCR2        0x%08x\n",
diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h
index 26d0177ca2..5f5c51d3d6 100644
--- a/drivers/pci/pcie_layerscape.h
+++ b/drivers/pci/pcie_layerscape.h
@@ -185,7 +185,7 @@  void ls_pcie_atu_outbound_set(struct ls_pcie *pcie, int idx, int type,
 			      u64 phys, u64 bus_addr, u64 size);
 void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, u32 pf, u32 vf_flag,
 			     int type, int idx, int bar, u64 phys);
-void ls_pcie_dump_atu(struct ls_pcie *pcie);
+void ls_pcie_dump_atu(struct ls_pcie *pcie, u32 win_num, u32 type);
 int ls_pcie_link_up(struct ls_pcie *pcie);
 void ls_pcie_dbi_ro_wr_en(struct ls_pcie *pcie);
 void ls_pcie_dbi_ro_wr_dis(struct ls_pcie *pcie);
diff --git a/drivers/pci/pcie_layerscape_ep.c b/drivers/pci/pcie_layerscape_ep.c
index cbf73e72c1..52d6397064 100644
--- a/drivers/pci/pcie_layerscape_ep.c
+++ b/drivers/pci/pcie_layerscape_ep.c
@@ -227,6 +227,9 @@  static void ls_pcie_setup_ep(struct ls_pcie_ep *pcie_ep)
 		ls_pcie_ep_setup_atu(pcie_ep, 0);
 	}
 
+	ls_pcie_dump_atu(pcie, PCIE_ATU_REGION_NUM_SRIOV,
+			 PCIE_ATU_REGION_INBOUND);
+
 	ls_pcie_ep_enable_cfg(pcie_ep);
 }
 
diff --git a/drivers/pci/pcie_layerscape_rc.c b/drivers/pci/pcie_layerscape_rc.c
index e922e5dbcd..25c6ddebce 100644
--- a/drivers/pci/pcie_layerscape_rc.c
+++ b/drivers/pci/pcie_layerscape_rc.c
@@ -115,7 +115,7 @@  static void ls_pcie_setup_atu(struct ls_pcie_rc *pcie_rc)
 					 pref->bus_start,
 					 pref->size);
 
-	ls_pcie_dump_atu(pcie);
+	ls_pcie_dump_atu(pcie, PCIE_ATU_REGION_NUM, PCIE_ATU_REGION_OUTBOUND);
 }
 
 /* Return 0 if the address is valid, -errno if not valid */