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[1/2] spi: fsl_qspi: Add support for i.MX7ULP

Message ID 1591689546-64136-1-git-send-email-ye.li@nxp.com
State Accepted
Commit 93d6c8f7b79786878f186b7e30676a52bba52860
Headers show
Series [1/2] spi: fsl_qspi: Add support for i.MX7ULP | expand

Commit Message

Ye Li June 9, 2020, 7:59 a.m. UTC 
Add compatible string and driver data for i.MX7ULP.
Meanwhile, the address set to SFA1AD/SFA2AD/SFB1AD/SFB2AD should
align with 1KB, because the lowest 10 bits are reserved by the
registers definition.
For i.MX7ULP which has only 128Bytes AHB buffer, must align it
when setting the registers and selecting cs.

Signed-off-by: Ye Li <ye.li at nxp.com>
Reviewed-by: Ashish Kumar <Ashish.Kumar at nxp.com>
Reviewed-by: Kuldeep Singh <kuldeep.singh at nxp.com>
---
 drivers/spi/fsl_qspi.c | 22 ++++++++++++++++------
 1 file changed, 16 insertions(+), 6 deletions(-)
diff mbox series

Patch

diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index e715f98..d9f531a 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -231,6 +231,15 @@  static const struct fsl_qspi_devtype_data imx6ul_data = {
 	.little_endian = true,
 };
 
+static const struct fsl_qspi_devtype_data imx7ulp_data = {
+	.rxfifo = SZ_64,
+	.txfifo = SZ_64,
+	.ahb_buf_size = SZ_128,
+	.quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK |
+		  QUADSPI_QUIRK_USE_TDH_SETTING,
+	.little_endian = true,
+};
+
 static const struct fsl_qspi_devtype_data ls1021a_data = {
 	.rxfifo = SZ_128,
 	.txfifo = SZ_64,
@@ -485,7 +494,7 @@  static void fsl_qspi_select_mem(struct fsl_qspi *q, struct spi_slave *slave)
 static void fsl_qspi_read_ahb(struct fsl_qspi *q, const struct spi_mem_op *op)
 {
 	memcpy_fromio(op->data.buf.in,
-		      q->ahb_addr + q->selected * q->devtype_data->ahb_buf_size,
+		      q->ahb_addr + q->selected * ALIGN(q->devtype_data->ahb_buf_size, 0x400),
 		      op->data.nbytes);
 }
 
@@ -589,7 +598,7 @@  static int fsl_qspi_exec_op(struct spi_slave *slave,
 		addr_offset = q->memmap_phy;
 
 	qspi_writel(q,
-		    q->selected * q->devtype_data->ahb_buf_size + addr_offset,
+		    q->selected * ALIGN(q->devtype_data->ahb_buf_size, 0x400) + addr_offset,
 		    base + QUADSPI_SFAR);
 
 	qspi_writel(q, qspi_readl(q, base + QUADSPI_MCR) |
@@ -695,13 +704,13 @@  static int fsl_qspi_default_setup(struct fsl_qspi *q)
 	 * We use ahb_buf_size for each chip and set SFA1AD, SFA2AD, SFB1AD,
 	 * SFB2AD accordingly.
 	 */
-	qspi_writel(q, q->devtype_data->ahb_buf_size + addr_offset,
+	qspi_writel(q, ALIGN(q->devtype_data->ahb_buf_size, 0x400) + addr_offset,
 		    base + QUADSPI_SFA1AD);
-	qspi_writel(q, q->devtype_data->ahb_buf_size * 2 + addr_offset,
+	qspi_writel(q, ALIGN(q->devtype_data->ahb_buf_size, 0x400) * 2 + addr_offset,
 		    base + QUADSPI_SFA2AD);
-	qspi_writel(q, q->devtype_data->ahb_buf_size * 3 + addr_offset,
+	qspi_writel(q, ALIGN(q->devtype_data->ahb_buf_size, 0x400) * 3 + addr_offset,
 		    base + QUADSPI_SFB1AD);
-	qspi_writel(q, q->devtype_data->ahb_buf_size * 4 + addr_offset,
+	qspi_writel(q, ALIGN(q->devtype_data->ahb_buf_size, 0x400) * 4 + addr_offset,
 		    base + QUADSPI_SFB2AD);
 
 	q->selected = -1;
@@ -799,6 +808,7 @@  static const struct udevice_id fsl_qspi_ids[] = {
 	{ .compatible = "fsl,imx6sx-qspi", .data = (ulong)&imx6sx_data, },
 	{ .compatible = "fsl,imx6ul-qspi", .data = (ulong)&imx6ul_data, },
 	{ .compatible = "fsl,imx7d-qspi", .data = (ulong)&imx7d_data, },
+	{ .compatible = "fsl,imx7ulp-qspi", .data = (ulong)&imx7ulp_data, },
 	{ .compatible = "fsl,ls1021a-qspi", .data = (ulong)&ls1021a_data, },
 	{ .compatible = "fsl,ls1088a-qspi", .data = (ulong)&ls1088a_data, },
 	{ .compatible = "fsl,ls2080a-qspi", .data = (ulong)&ls2080a_data, },