| Message ID | 20200625105029.3700-1-festevam@gmail.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | ARM: dts: imx6q-tbs2910: Fix Ethernet regression | expand |
diff --git a/arch/arm/dts/imx6q-tbs2910.dts b/arch/arm/dts/imx6q-tbs2910.dts index cc5df37b46..eb08801044 100644 --- a/arch/arm/dts/imx6q-tbs2910.dts +++ b/arch/arm/dts/imx6q-tbs2910.dts @@ -107,7 +107,19 @@ pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii-id"; phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + phy-handle = <&phy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy: ethernet-phy at 4 { + reg = <4>; + qca,clk-out-frequency = <125000000>; + }; + }; }; &hdmi {
Since commit: commit 6333cbb3817ed551cd7d4e92f7359c73ccc567fc Author: Michael Walle <michael at walle.cc> Date: Thu May 7 00:11:58 2020 +0200 phy: atheros: ar8035: remove static clock config We can configure the clock output in the device tree. Disable the hardcoded one in here. This is highly board-specific and should have never been enabled in the PHY driver. If bisecting shows that this commit breaks your board it probably depends on the clock output of your Atheros AR8035 PHY. Please have a look at doc/device-tree-bindings/net/phy/atheros.txt. You need to set "clk-out-frequency = <125000000>" because that value was the hardcoded value until this commit. Signed-off-by: Michael Walle <michael at walle.cc> Acked-by: Joe Hershberger <joe.hershberger at ni.com> , the clock output setting for the AR803x driver is removed from being hardcoded in the PHY driver and should be passed via device tree instead. Update the device tree with the "qca,clk-out-frequency" property so that Ethernet can work again. Reported-by: Soeren Moch <smoch at web.de> Signed-off-by: Fabio Estevam <festevam at gmail.com> --- arch/arm/dts/imx6q-tbs2910.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+)