@@ -7,6 +7,7 @@
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/dma-buf.h>
+#include <linux/regulator/consumer.h>
#include <drm/drm_device.h>
#include <drm/drm_fb_cma_helper.h>
@@ -873,6 +874,14 @@ static void mcde_display_enable(struct drm_simple_display_pipe *pipe,
u32 formatter_frame;
u32 pkt_div;
u32 val;
+ int ret;
+
+ /* This powers up the entire MCDE block and the DSI hardware */
+ ret = regulator_enable(mcde->epod);
+ if (ret) {
+ dev_err(drm->dev, "can't re-enable EPOD regulator\n");
+ return;
+ }
dev_info(drm->dev, "enable MCDE, %d x %d format %s\n",
mode->hdisplay, mode->vdisplay,
@@ -1008,6 +1017,7 @@ static void mcde_display_disable(struct drm_simple_display_pipe *pipe)
struct drm_device *drm = crtc->dev;
struct mcde *mcde = to_mcde(drm);
struct drm_pending_vblank_event *event;
+ int ret;
drm_crtc_vblank_off(crtc);
@@ -1023,6 +1033,12 @@ static void mcde_display_disable(struct drm_simple_display_pipe *pipe)
spin_unlock_irq(&crtc->dev->event_lock);
}
+ ret = regulator_disable(mcde->epod);
+ if (ret)
+ dev_err(drm->dev, "can't disable EPOD regulator\n");
+ /* Make sure we are powered down (before we may power up again) */
+ usleep_range(1000, 1500);
+
dev_info(drm->dev, "MCDE display is disabled\n");
}
@@ -63,6 +63,7 @@
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
#include <linux/slab.h>
+#include <linux/delay.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_bridge.h>
@@ -468,6 +469,19 @@ static int mcde_probe(struct platform_device *pdev)
dev_err(dev, "failed to add component master\n");
goto clk_disable;
}
+
+ /*
+ * Perform an invasive reset of the MCDE and all blocks by
+ * cutting the power to the subsystem, then bring it back up
+ * later when we enable the display.
+ */
+ ret = regulator_disable(mcde->epod);
+ if (ret) {
+ dev_err(dev, "can't disable EPOD regulator\n");
+ return ret;
+ }
+ usleep_range(1000, 1500);
+
return 0;
clk_disable:
@@ -902,6 +902,21 @@ static void mcde_dsi_bridge_pre_enable(struct drm_bridge *bridge)
dev_info(d->dev, "DSI HS clock rate %lu Hz\n",
d->hs_freq);
+ /* Assert RESET through the PRCMU, active low */
+ /* FIXME: which DSI block? */
+ regmap_update_bits(d->prcmu, PRCM_DSI_SW_RESET,
+ PRCM_DSI_SW_RESET_DSI0_SW_RESETN, 0);
+
+ usleep_range(100, 200);
+
+ /* De-assert RESET again */
+ regmap_update_bits(d->prcmu, PRCM_DSI_SW_RESET,
+ PRCM_DSI_SW_RESET_DSI0_SW_RESETN,
+ PRCM_DSI_SW_RESET_DSI0_SW_RESETN);
+
+ /* Start up the hardware */
+ mcde_dsi_start(d);
+
if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
/* Put IF1 into video mode */
val = readl(d->regs + DSI_MCTL_MAIN_DATA_CTL);
@@ -998,9 +1013,6 @@ static void mcde_dsi_bridge_disable(struct drm_bridge *bridge)
struct mcde_dsi *d = bridge_to_mcde_dsi(bridge);
u32 val;
- /* Disable all error interrupts */
- writel(0, d->regs + DSI_VID_MODE_STS_CTL);
-
if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
/* Stop video mode */
val = readl(d->regs + DSI_MCTL_MAIN_DATA_CTL);
@@ -1011,8 +1023,20 @@ static void mcde_dsi_bridge_disable(struct drm_bridge *bridge)
/* Stop command mode */
mcde_dsi_wait_for_command_mode_stop(d);
}
+}
+
+static void mcde_dsi_bridge_post_disable(struct drm_bridge *bridge)
+{
+ struct mcde_dsi *d = bridge_to_mcde_dsi(bridge);
+
+ /*
+ * Stop clocks and terminate any DSI traffic here so the panel can
+ * send commands to shut down the display using DSI direct write until
+ * this point.
+ */
- /* Stop clocks */
+ /* Disable all error interrupts */
+ writel(0, d->regs + DSI_VID_MODE_STS_CTL);
clk_disable_unprepare(d->hs_clk);
clk_disable_unprepare(d->lp_clk);
}
@@ -1045,6 +1069,7 @@ static const struct drm_bridge_funcs mcde_dsi_bridge_funcs = {
.disable = mcde_dsi_bridge_disable,
.enable = mcde_dsi_bridge_enable,
.pre_enable = mcde_dsi_bridge_pre_enable,
+ .post_disable = mcde_dsi_bridge_post_disable,
};
static int mcde_dsi_bind(struct device *dev, struct device *master,
@@ -1080,21 +1105,6 @@ static int mcde_dsi_bind(struct device *dev, struct device *master,
return PTR_ERR(d->lp_clk);
}
- /* Assert RESET through the PRCMU, active low */
- /* FIXME: which DSI block? */
- regmap_update_bits(d->prcmu, PRCM_DSI_SW_RESET,
- PRCM_DSI_SW_RESET_DSI0_SW_RESETN, 0);
-
- usleep_range(100, 200);
-
- /* De-assert RESET again */
- regmap_update_bits(d->prcmu, PRCM_DSI_SW_RESET,
- PRCM_DSI_SW_RESET_DSI0_SW_RESETN,
- PRCM_DSI_SW_RESET_DSI0_SW_RESETN);
-
- /* Start up the hardware */
- mcde_dsi_start(d);
-
/* Look for a panel as a child to this node */
for_each_available_child_of_node(dev->of_node, child) {
panel = of_drm_find_panel(child);
To make sure that the MCDE is in a reasonable state during set-up, perform a reset by power cycling the block by dropping the on-chip regulator reference after probe. The display subsystem (DSS) has no dedicated reset line so dropping the EPOD regulator is the only real way of resetting it. We introduce code to enable and disable the regulator in the display enable/disable callbacks. When we drop the power to the whole display subsystem, not only MCDE but also the DSI links lose their state. Therefore we move the DSI block reset and hardware initialization code to the mcde_dsi_bridge_pre_enable() callback so this happens every time we start up the bridge, as we may have lost the power. We move the final disablement of the interrupts and clocks to the mcde_dsi_bridge_post_disable() callback rather than have it in the mcde_dsi_bridge_disable() callback, as some control messages may still be sent over the DSI host after the bridge has been shut down. This (together with a patch for the corresponding panel) makes the Samsung GT-S7710 successfully disable and re-enable its display, cutting all power while disabled and re-initializing the hardware when coming back up. Cc: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> --- drivers/gpu/drm/mcde/mcde_display.c | 16 ++++++++++ drivers/gpu/drm/mcde/mcde_drv.c | 14 +++++++++ drivers/gpu/drm/mcde/mcde_dsi.c | 48 +++++++++++++++++------------ 3 files changed, 59 insertions(+), 19 deletions(-) -- 2.26.2 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel