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[5/6] arm64: dts: ti: k3-j7200-common-proc-board: Configure the SERDES lane function

Message ID 20200907103810.9870-6-rogerq@ti.com
State Superseded
Headers show
Series None | expand

Commit Message

Roger Quadros Sept. 7, 2020, 10:38 a.m. UTC 
From: Kishon Vijay Abraham I <kishon@ti.com>


First two lanes of SERDES is connected to PCIe, third lane is connected
to QSGMII and the last lane is connected to USB. However Cadence torrent SERDES
doesn't support more than 2 protocols at the same time. Configure it only for
PCIe and QSGMII.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>

Signed-off-by: Roger Quadros <rogerq@ti.com>

---
 arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts | 6 ++++++
 1 file changed, 6 insertions(+)

-- 
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diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
index 8e534ef8a3f5..0ecaba600704 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
@@ -6,6 +6,7 @@ 
 /dts-v1/;
 
 #include "k3-j7200-som-p0.dtsi"
+#include <dt-bindings/mux/mux-j7200-wiz.h>
 
 / {
 	chosen {
@@ -139,3 +140,8 @@ 
 	ti,driver-strength-ohm = <50>;
 	disable-wp;
 };
+
+&serdes_ln_ctrl {
+	idle-states = <SERDES0_LANE0_PCIE1_LANE0>, <SERDES0_LANE1_PCIE1_LANE1>,
+		      <SERDES0_LANE2_QSGMII_LANE1>, <SERDES0_LANE3_IP4_UNUSED>;
+};