Message ID | 1393439997-26936-5-git-send-email-stefano.stabellini@eu.citrix.com |
---|---|
State | New |
Headers | show
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diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index 15e5f91..371ebd8 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -789,6 +789,12 @@ void gic_inject(void) vgic_vcpu_inject_irq(current, current->domain->arch.evtchn_irq); gic_restore_pending_irqs(current); + + if ( !list_empty(¤t->arch.vgic.lr_pending) && + this_cpu(lr_mask) == ((1 << nr_lrs) - 1) ) + GICH[GICH_HCR] |= GICH_HCR_UIE; + else + GICH[GICH_HCR] &= ~GICH_HCR_UIE; } int gic_route_irq_to_guest(struct domain *d, const struct dt_irq *irq,
On return to guest, if there are no free LRs and we still have more interrupt to inject, set GICH_HCR_UIE so that we are going to receive a maintenance interrupt when no pending interrupts are present in the LR registers. The maintenance interrupt handler won't do anything anymore, but receiving the interrupt is going to cause gic_inject to be called on return to guest that is going to clear the old LRs and inject new interrupts. Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> --- Changes in v2: - disable/enable the GICH_HCR_UIE bit in GICH_HCR; - only enable GICH_HCR_UIE if this_cpu(lr_mask) == ((1 << nr_lrs) - 1). --- xen/arch/arm/gic.c | 6 ++++++ 1 file changed, 6 insertions(+)