| Message ID | 20200928171539.788309-3-f4bug@amsat.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | hw/mips: Set CPU frequency | expand |
On Monday, September 28, 2020, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote: > The get_random() helper uses the CP0_Wired register, which is > unrelated to the CP0_Count register use as timer. > Commit e16fe40c872 ("Move the MIPS CPU timer in a separate file") > incorrectly moved this get_random() helper with timer specific > code. Move it back to generic CP0 helpers. > > Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> > --- Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> > target/mips/internal.h | 2 +- > target/mips/cp0_helper.c | 25 +++++++++++++++++++++++++ > target/mips/cp0_timer.c | 25 ------------------------- > 3 files changed, 26 insertions(+), 26 deletions(-) > > diff --git a/target/mips/internal.h b/target/mips/internal.h > index 7f159a9230c..087cabaa6d4 100644 > --- a/target/mips/internal.h > +++ b/target/mips/internal.h > @@ -144,6 +144,7 @@ void r4k_helper_tlbr(CPUMIPSState *env); > void r4k_helper_tlbinv(CPUMIPSState *env); > void r4k_helper_tlbinvf(CPUMIPSState *env); > void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra); > +uint32_t cpu_mips_get_random(CPUMIPSState *env); > > void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, > vaddr addr, unsigned size, > @@ -209,7 +210,6 @@ void cpu_state_reset(CPUMIPSState *s); > void cpu_mips_realize_env(CPUMIPSState *env); > > /* cp0_timer.c */ > -uint32_t cpu_mips_get_random(CPUMIPSState *env); > uint32_t cpu_mips_get_count(CPUMIPSState *env); > void cpu_mips_store_count(CPUMIPSState *env, uint32_t value); > void cpu_mips_store_compare(CPUMIPSState *env, uint32_t value); > diff --git a/target/mips/cp0_helper.c b/target/mips/cp0_helper.c > index de64add038b..12143ac55b9 100644 > --- a/target/mips/cp0_helper.c > +++ b/target/mips/cp0_helper.c > @@ -203,6 +203,31 @@ static void sync_c0_entryhi(CPUMIPSState *cpu, int tc) > *tcst |= asid; > } > > +/* XXX: do not use a global */ > +uint32_t cpu_mips_get_random(CPUMIPSState *env) > +{ > + static uint32_t seed = 1; > + static uint32_t prev_idx; > + uint32_t idx; > + uint32_t nb_rand_tlb = env->tlb->nb_tlb - env->CP0_Wired; > + > + if (nb_rand_tlb == 1) { > + return env->tlb->nb_tlb - 1; > + } > + > + /* Don't return same value twice, so get another value */ > + do { > + /* > + * Use a simple algorithm of Linear Congruential Generator > + * from ISO/IEC 9899 standard. > + */ > + seed = 1103515245 * seed + 12345; > + idx = (seed >> 16) % nb_rand_tlb + env->CP0_Wired; > + } while (idx == prev_idx); > + prev_idx = idx; > + return idx; > +} > + > /* CP0 helpers */ > target_ulong helper_mfc0_mvpcontrol(CPUMIPSState *env) > { > diff --git a/target/mips/cp0_timer.c b/target/mips/cp0_timer.c > index bd7efb152dd..9c38e9da1c8 100644 > --- a/target/mips/cp0_timer.c > +++ b/target/mips/cp0_timer.c > @@ -29,31 +29,6 @@ > > #define TIMER_PERIOD 10 /* 10 ns period for 100 Mhz frequency */ > > -/* XXX: do not use a global */ > -uint32_t cpu_mips_get_random(CPUMIPSState *env) > -{ > - static uint32_t seed = 1; > - static uint32_t prev_idx = 0; > - uint32_t idx; > - uint32_t nb_rand_tlb = env->tlb->nb_tlb - env->CP0_Wired; > - > - if (nb_rand_tlb == 1) { > - return env->tlb->nb_tlb - 1; > - } > - > - /* Don't return same value twice, so get another value */ > - do { > - /* > - * Use a simple algorithm of Linear Congruential Generator > - * from ISO/IEC 9899 standard. > - */ > - seed = 1103515245 * seed + 12345; > - idx = (seed >> 16) % nb_rand_tlb + env->CP0_Wired; > - } while (idx == prev_idx); > - prev_idx = idx; > - return idx; > -} > - > /* MIPS R4K timer */ > static void cpu_mips_timer_update(CPUMIPSState *env) > { > -- > 2.26.2 > > <br><br>On Monday, September 28, 2020, Philippe Mathieu-Daudé <<a href="mailto:f4bug@amsat.org">f4bug@amsat.org</a>> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">The get_random() helper uses the CP0_Wired register, which is<br> unrelated to the CP0_Count register use as timer.<br> Commit e16fe40c872 ("Move the MIPS CPU timer in a separate file")<br> incorrectly moved this get_random() helper with timer specific<br> code. Move it back to generic CP0 helpers.<br> <br> Signed-off-by: Philippe Mathieu-Daudé <<a href="mailto:f4bug@amsat.org">f4bug@amsat.org</a>><br> ---</blockquote><div><br></div><div><span style="color:rgb(34,34,34);font-size:14px;line-height:22.1200008392334px">Reviewed-by: Aleksandar Markovic <</span><a href="mailto:aleksandar.qemu.devel@gmail.com" target="_blank" style="font-size:14px;line-height:22.1200008392334px">aleksandar.qemu.devel@gmail.c<wbr>om</a><span style="color:rgb(34,34,34);font-size:14px;line-height:22.1200008392334px">></span><br></div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"> target/mips/internal.h | 2 +-<br> target/mips/cp0_helper.c | 25 +++++++++++++++++++++++++<br> target/mips/cp0_timer.c | 25 -------------------------<br> 3 files changed, 26 insertions(+), 26 deletions(-)<br> <br> diff --git a/target/mips/internal.h b/target/mips/internal.h<br> index 7f159a9230c..087cabaa6d4 100644<br> --- a/target/mips/internal.h<br> +++ b/target/mips/internal.h<br> @@ -144,6 +144,7 @@ void r4k_helper_tlbr(CPUMIPSState *env);<br> void r4k_helper_tlbinv(CPUMIPSState *env);<br> void r4k_helper_tlbinvf(<wbr>CPUMIPSState *env);<br> void r4k_invalidate_tlb(<wbr>CPUMIPSState *env, int idx, int use_extra);<br> +uint32_t cpu_mips_get_random(<wbr>CPUMIPSState *env);<br> <br> void mips_cpu_do_transaction_<wbr>failed(CPUState *cs, hwaddr physaddr,<br> vaddr addr, unsigned size,<br> @@ -209,7 +210,6 @@ void cpu_state_reset(CPUMIPSState *s);<br> void cpu_mips_realize_env(<wbr>CPUMIPSState *env);<br> <br> /* cp0_timer.c */<br> -uint32_t cpu_mips_get_random(<wbr>CPUMIPSState *env);<br> uint32_t cpu_mips_get_count(<wbr>CPUMIPSState *env);<br> void cpu_mips_store_count(<wbr>CPUMIPSState *env, uint32_t value);<br> void cpu_mips_store_compare(<wbr>CPUMIPSState *env, uint32_t value);<br> diff --git a/target/mips/cp0_helper.c b/target/mips/cp0_helper.c<br> index de64add038b..12143ac55b9 100644<br> --- a/target/mips/cp0_helper.c<br> +++ b/target/mips/cp0_helper.c<br> @@ -203,6 +203,31 @@ static void sync_c0_entryhi(CPUMIPSState *cpu, int tc)<br> *tcst |= asid;<br> }<br> <br> +/* XXX: do not use a global */<br> +uint32_t cpu_mips_get_random(<wbr>CPUMIPSState *env)<br> +{<br> + static uint32_t seed = 1;<br> + static uint32_t prev_idx;<br> + uint32_t idx;<br> + uint32_t nb_rand_tlb = env->tlb->nb_tlb - env->CP0_Wired;<br> +<br> + if (nb_rand_tlb == 1) {<br> + return env->tlb->nb_tlb - 1;<br> + }<br> +<br> + /* Don't return same value twice, so get another value */<br> + do {<br> + /*<br> + * Use a simple algorithm of Linear Congruential Generator<br> + * from ISO/IEC 9899 standard.<br> + */<br> + seed = 1103515245 * seed + 12345;<br> + idx = (seed >> 16) % nb_rand_tlb + env->CP0_Wired;<br> + } while (idx == prev_idx);<br> + prev_idx = idx;<br> + return idx;<br> +}<br> +<br> /* CP0 helpers */<br> target_ulong helper_mfc0_mvpcontrol(<wbr>CPUMIPSState *env)<br> {<br> diff --git a/target/mips/cp0_timer.c b/target/mips/cp0_timer.c<br> index bd7efb152dd..9c38e9da1c8 100644<br> --- a/target/mips/cp0_timer.c<br> +++ b/target/mips/cp0_timer.c<br> @@ -29,31 +29,6 @@<br> <br> #define TIMER_PERIOD 10 /* 10 ns period for 100 Mhz frequency */<br> <br> -/* XXX: do not use a global */<br> -uint32_t cpu_mips_get_random(<wbr>CPUMIPSState *env)<br> -{<br> - static uint32_t seed = 1;<br> - static uint32_t prev_idx = 0;<br> - uint32_t idx;<br> - uint32_t nb_rand_tlb = env->tlb->nb_tlb - env->CP0_Wired;<br> -<br> - if (nb_rand_tlb == 1) {<br> - return env->tlb->nb_tlb - 1;<br> - }<br> -<br> - /* Don't return same value twice, so get another value */<br> - do {<br> - /*<br> - * Use a simple algorithm of Linear Congruential Generator<br> - * from ISO/IEC 9899 standard.<br> - */<br> - seed = 1103515245 * seed + 12345;<br> - idx = (seed >> 16) % nb_rand_tlb + env->CP0_Wired;<br> - } while (idx == prev_idx);<br> - prev_idx = idx;<br> - return idx;<br> -}<br> -<br> /* MIPS R4K timer */<br> static void cpu_mips_timer_update(<wbr>CPUMIPSState *env)<br> {<br> -- <br> 2.26.2<br> <br> </blockquote>
diff --git a/target/mips/internal.h b/target/mips/internal.h index 7f159a9230c..087cabaa6d4 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -144,6 +144,7 @@ void r4k_helper_tlbr(CPUMIPSState *env); void r4k_helper_tlbinv(CPUMIPSState *env); void r4k_helper_tlbinvf(CPUMIPSState *env); void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra); +uint32_t cpu_mips_get_random(CPUMIPSState *env); void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, unsigned size, @@ -209,7 +210,6 @@ void cpu_state_reset(CPUMIPSState *s); void cpu_mips_realize_env(CPUMIPSState *env); /* cp0_timer.c */ -uint32_t cpu_mips_get_random(CPUMIPSState *env); uint32_t cpu_mips_get_count(CPUMIPSState *env); void cpu_mips_store_count(CPUMIPSState *env, uint32_t value); void cpu_mips_store_compare(CPUMIPSState *env, uint32_t value); diff --git a/target/mips/cp0_helper.c b/target/mips/cp0_helper.c index de64add038b..12143ac55b9 100644 --- a/target/mips/cp0_helper.c +++ b/target/mips/cp0_helper.c @@ -203,6 +203,31 @@ static void sync_c0_entryhi(CPUMIPSState *cpu, int tc) *tcst |= asid; } +/* XXX: do not use a global */ +uint32_t cpu_mips_get_random(CPUMIPSState *env) +{ + static uint32_t seed = 1; + static uint32_t prev_idx; + uint32_t idx; + uint32_t nb_rand_tlb = env->tlb->nb_tlb - env->CP0_Wired; + + if (nb_rand_tlb == 1) { + return env->tlb->nb_tlb - 1; + } + + /* Don't return same value twice, so get another value */ + do { + /* + * Use a simple algorithm of Linear Congruential Generator + * from ISO/IEC 9899 standard. + */ + seed = 1103515245 * seed + 12345; + idx = (seed >> 16) % nb_rand_tlb + env->CP0_Wired; + } while (idx == prev_idx); + prev_idx = idx; + return idx; +} + /* CP0 helpers */ target_ulong helper_mfc0_mvpcontrol(CPUMIPSState *env) { diff --git a/target/mips/cp0_timer.c b/target/mips/cp0_timer.c index bd7efb152dd..9c38e9da1c8 100644 --- a/target/mips/cp0_timer.c +++ b/target/mips/cp0_timer.c @@ -29,31 +29,6 @@ #define TIMER_PERIOD 10 /* 10 ns period for 100 Mhz frequency */ -/* XXX: do not use a global */ -uint32_t cpu_mips_get_random(CPUMIPSState *env) -{ - static uint32_t seed = 1; - static uint32_t prev_idx = 0; - uint32_t idx; - uint32_t nb_rand_tlb = env->tlb->nb_tlb - env->CP0_Wired; - - if (nb_rand_tlb == 1) { - return env->tlb->nb_tlb - 1; - } - - /* Don't return same value twice, so get another value */ - do { - /* - * Use a simple algorithm of Linear Congruential Generator - * from ISO/IEC 9899 standard. - */ - seed = 1103515245 * seed + 12345; - idx = (seed >> 16) % nb_rand_tlb + env->CP0_Wired; - } while (idx == prev_idx); - prev_idx = idx; - return idx; -} - /* MIPS R4K timer */ static void cpu_mips_timer_update(CPUMIPSState *env) {
The get_random() helper uses the CP0_Wired register, which is unrelated to the CP0_Count register use as timer. Commit e16fe40c872 ("Move the MIPS CPU timer in a separate file") incorrectly moved this get_random() helper with timer specific code. Move it back to generic CP0 helpers. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> --- target/mips/internal.h | 2 +- target/mips/cp0_helper.c | 25 +++++++++++++++++++++++++ target/mips/cp0_timer.c | 25 ------------------------- 3 files changed, 26 insertions(+), 26 deletions(-)