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[RFC,1/4] ARM: DT: QCOM: apq8064: fix the memory range for sdcc node.

Message ID 1400269543-15449-1-git-send-email-srinivas.kandagatla@linaro.org
State New
Headers show

Commit Message

Srinivas Kandagatla May 16, 2014, 7:45 p.m. UTC 
From: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>

This patch fixes the range of iomemory for sdcc controller, it is now
set to 0x2000 so that the mmci driver could talk to dml hardware as well.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
---
 arch/arm/boot/dts/qcom-apq8064.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
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Patch

diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index 640fb1d..2a6cd09 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -167,7 +167,7 @@ 
 				status		= "disabled";
 				compatible	= "arm,pl18x", "arm,primecell";
 				arm,primecell-periphid = <0x00051180>;
-				reg		= <0x12400000 0x8000>;
+				reg		= <0x12400000 0x2000>;
 				interrupts	= <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 				interrupt-names	= "cmd_irq";
 				clocks		= <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
@@ -184,7 +184,7 @@ 
 				compatible	= "arm,pl18x", "arm,primecell";
 				arm,primecell-periphid = <0x00051180>;
 				status		= "disabled";
-				reg		= <0x12180000 0x8000>;
+				reg		= <0x12180000 0x2000>;
 				interrupts	= <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 				interrupt-names	= "cmd_irq";
 				clocks		= <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;