| Message ID | 1401208114-22404-1-git-send-email-peter.maydell@linaro.org |
|---|---|
| State | Not Applicable |
| Headers | show |
On 27 May 2014 17:28, Peter Maydell <peter.maydell@linaro.org> wrote: > This is mostly Edgar's patchset, which I wanted to get upstream > so we can rebase the other trustzone related patches on top of it. > > thanks > -- PMM > > The following changes since commit 93f94f9018229f146ed6bbe9e5ff72d67e4bd7ab: > > Merge remote-tracking branch 'remotes/rth/fix-tci' into staging (2014-05-27 14:44:04 +0100) > > are available in the git repository at: > > > git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20140527 > > for you to fetch changes up to a1ba125c0ca64b604484ddc104e533546d92088a: > > target-arm: A64: Register VBAR_EL3 (2014-05-27 17:09:55 +0100) > > ---------------------------------------------------------------- > target-arm: > * Preliminary restructuring for EL2/EL3 support > * improve CPACR handling > * fix pxa2xx_lcd palette formats > * update highbank/midway maintainer Applied, thanks. -- PMM
This is mostly Edgar's patchset, which I wanted to get upstream so we can rebase the other trustzone related patches on top of it. thanks -- PMM The following changes since commit 93f94f9018229f146ed6bbe9e5ff72d67e4bd7ab: Merge remote-tracking branch 'remotes/rth/fix-tci' into staging (2014-05-27 14:44:04 +0100) are available in the git repository at: git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20140527 for you to fetch changes up to a1ba125c0ca64b604484ddc104e533546d92088a: target-arm: A64: Register VBAR_EL3 (2014-05-27 17:09:55 +0100) ---------------------------------------------------------------- target-arm: * Preliminary restructuring for EL2/EL3 support * improve CPACR handling * fix pxa2xx_lcd palette formats * update highbank/midway maintainer ---------------------------------------------------------------- Edgar E. Iglesias (21): target-arm: Move get_mem_index to translate.h target-arm: A32: Use get_mem_index for load/stores target-arm: Use a 1:1 mapping between EL and MMU index target-arm: Make elr_el1 an array target-arm: Make esr_el1 an array target-arm: c12_vbar -> vbar_el[] target-arm: A64: Add SP entries for EL2 and 3 target-arm: A64: Add ELR entries for EL2 and 3 target-arm: Add SPSR entries for EL2/HYP and EL3/MON target-arm: A64: Introduce aarch64_banked_spsr_index() target-arm: Add a feature flag for EL2 target-arm: Add a feature flag for EL3 target-arm: Register EL2 versions of ELR and SPSR target-arm: Register EL3 versions of ELR and SPSR target-arm: A64: Forbid ERET to higher or unimplemented ELs target-arm: A64: Trap ERET from EL0 at translation time target-arm: A64: Generalize ERET to various ELs target-arm: A64: Generalize update_spsel for the various ELs target-arm: Make vbar_write writeback to any CPREG target-arm: A64: Register VBAR_EL2 target-arm: A64: Register VBAR_EL3 Fabian Aggeler (1): target-arm: implement CPACR register logic for ARMv7 Peter Maydell (3): hw/display/pxa2xx_lcd: Fix 16bpp+alpha and 18bpp+alpha palette formats target-arm/translate.c: Clean up mmu index handling for ldrt/strt target-arm/translate.c: Use get_mem_index() for SRS memory accesses Rob Herring (1): MAINTAINERS: update Calxeda Highbank maintainer and status MAINTAINERS | 4 +- hw/display/pxa2xx_lcd.c | 16 +-- target-arm/cpu.h | 22 ++-- target-arm/helper-a64.c | 12 +-- target-arm/helper.c | 113 +++++++++++++++++--- target-arm/internals.h | 25 ++++- target-arm/kvm64.c | 4 +- target-arm/machine.c | 10 +- target-arm/op_helper.c | 20 ++-- target-arm/translate-a64.c | 13 +-- target-arm/translate.c | 249 +++++++++++++++++++++++---------------------- target-arm/translate.h | 5 + 12 files changed, 305 insertions(+), 188 deletions(-)