| Message ID | 20200916071722.28772-3-peng.fan@nxp.com |
|---|---|
| State | New |
| Headers | show
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Wed, 16 Sep 2020 06:53:12 +0000 From: peng.fan@nxp.com To: sbabic@denx.de, festevam@gmail.com Cc: uboot-imx@nxp.com, u-boot@lists.denx.de, Peng Fan <peng.fan@nxp.com>, Ye Li <ye.li@nxp.com> Subject: [PATCH 3/5] imx8mq: fix SSCG_PLL_REFCLK_SEL_x Date: Wed, 16 Sep 2020 15:17:20 +0800 Message-Id: <20200916071722.28772-3-peng.fan@nxp.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200916071722.28772-1-peng.fan@nxp.com> References: <20200916071722.28772-1-peng.fan@nxp.com> Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: SG2PR06CA0230.apcprd06.prod.outlook.com (2603:1096:4:ac::14) To DB6PR0402MB2760.eurprd04.prod.outlook.com (2603:10a6:4:a1::14) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from linux-1xn6.ap.freescale.net (119.31.174.71) by SG2PR06CA0230.apcprd06.prod.outlook.com (2603:1096:4:ac::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3391.11 via Frontend Transport; Wed, 16 Sep 2020 06:53:09 +0000 X-Mailer: git-send-email 2.28.0 X-Originating-IP: [119.31.174.71] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 47c989a7-579a-4894-1b36-08d85a0d2d94 X-MS-TrafficTypeDiagnostic: DB7PR04MB4762: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: <DB7PR04MB4762D5C4402AA154DA642F5988210@DB7PR04MB4762.eurprd04.prod.outlook.com> X-MS-Oob-TLC-OOBClassifiers: OLM:913; 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| Series | [1/5] imx7: ccm: correct target interface num | expand |
diff --git a/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h b/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h index 7109d334fa..340a61e55b 100644 --- a/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h +++ b/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h @@ -358,10 +358,10 @@ enum clk_src_index { #define SSCG_PLL_LOCK_SEL_MASK BIT(3) #define SSCG_PLL_COUNTCLK_SEL_MASK BIT(2) #define SSCG_PLL_REFCLK_SEL_MASK 0x3 -#define SSCG_PLL_REFCLK_SEL_OSC_25M (0 << 16) -#define SSCG_PLL_REFCLK_SEL_OSC_27M BIT(16) -#define SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M (2 << 16) -#define SSCG_PLL_REFCLK_SEL_CLK_PN (3 << 16) +#define SSCG_PLL_REFCLK_SEL_OSC_25M (0) +#define SSCG_PLL_REFCLK_SEL_OSC_27M (1) +#define SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M (2) +#define SSCG_PLL_REFCLK_SEL_CLK_PN (3) #define SSCG_PLL_SSDS_MASK BIT(8) #define SSCG_PLL_SSMD_MASK (0x7 << 5)