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[11/11] arm64: dts: hisilicon: list all clocks required by snps-dw-apb-uart.yaml

Message ID 20201012131739.1655-12-thunder.leizhen@huawei.com
State Accepted
Commit c4cbd0356c60c71dd717bd0c3825bb0646a6d347
Headers show
Series clean up some Hisilicon-related errors detected by DT schema on arm64 | expand

Commit Message

Leizhen (ThunderTown) Oct. 12, 2020, 1:17 p.m. UTC 
The snps,dw-apb-uart binding need to specify two clocks: "baudclk",
"apb_pclk". But only "apb_pclk" is specified now. Because the driver
preferentially matches the first clock. Otherwise, it matches the second
clock instead of both clocks. So both of them use the same clock don't
change the function.

Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>

---
 arch/arm64/boot/dts/hisilicon/hip05.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

-- 
1.8.3
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi
index 26caf09e9511b3c..c073d6d8b55c0b4 100644
--- a/arch/arm64/boot/dts/hisilicon/hip05.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi
@@ -300,8 +300,8 @@ 
 			compatible = "snps,dw-apb-uart";
 			reg = <0x0 0x80300000 0x0 0x10000>;
 			interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&refclk200mhz>;
-			clock-names = "apb_pclk";
+			clocks = <&refclk200mhz>, <&refclk200mhz>;
+			clock-names = "baudclk", "apb_pclk";
 			reg-shift = <2>;
 			reg-io-width = <4>;
 			status = "disabled";
@@ -311,8 +311,8 @@ 
 			compatible = "snps,dw-apb-uart";
 			reg = <0x0 0x80310000 0x0 0x10000>;
 			interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&refclk200mhz>;
-			clock-names = "apb_pclk";
+			clocks = <&refclk200mhz>, <&refclk200mhz>;
+			clock-names = "baudclk", "apb_pclk";
 			reg-shift = <2>;
 			reg-io-width = <4>;
 			status = "disabled";