diff mbox series

[v1,2/2] gpio: tegra: Use raw_spinlock

Message ID 20201104132624.17168-2-digetx@gmail.com
State New
Headers show
Series [v1,1/2] gpio: tegra: Add lockdep class | expand

Commit Message

Dmitry Osipenko Nov. 4, 2020, 1:26 p.m. UTC 
Use raw_spinlock in order to fix spurious messages about invalid context
when spinlock debugging is enabled. This happens because there is a legit
nested raw_spinlock->spinlock locking which debug code can't recognize and
handle.

 [ BUG: Invalid wait context ]
 ...
  (dump_stack) from (__lock_acquire)
  (__lock_acquire) from (lock_acquire)
  (lock_acquire) from (_raw_spin_lock_irqsave)
  (_raw_spin_lock_irqsave) from (tegra_gpio_irq_set_type)
  (tegra_gpio_irq_set_type) from (__irq_set_trigger)
  (__irq_set_trigger) from (__setup_irq)
  (__setup_irq) from (request_threaded_irq)
  (request_threaded_irq) from (devm_request_threaded_irq)
  (devm_request_threaded_irq) from (elants_i2c_probe)
  (elants_i2c_probe) from (i2c_device_probe)
 ...

Tested-by: Peter Geis <pgwipeout@gmail.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
 drivers/gpio/gpio-tegra.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

Comments

Andy Shevchenko Nov. 4, 2020, 2:47 p.m. UTC | #1 
On Wed, Nov 4, 2020 at 3:27 PM Dmitry Osipenko <digetx@gmail.com> wrote:
>

> Use raw_spinlock in order to fix spurious messages about invalid context

> when spinlock debugging is enabled. This happens because there is a legit

> nested raw_spinlock->spinlock locking which debug code can't recognize and

> handle.


This sounds like papering over a problem that exists somewhere else.

What I would rather make as a selling point is that raw spin locks are
necessary to be in the RT kernel for IRQ chips.

> Tested-by: Peter Geis <pgwipeout@gmail.com>

> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>


-- 
With Best Regards,
Andy Shevchenko
Dmitry Osipenko Nov. 4, 2020, 3:03 p.m. UTC | #2 
04.11.2020 17:47, Andy Shevchenko пишет:
> On Wed, Nov 4, 2020 at 3:27 PM Dmitry Osipenko <digetx@gmail.com> wrote:

>>

>> Use raw_spinlock in order to fix spurious messages about invalid context

>> when spinlock debugging is enabled. This happens because there is a legit

>> nested raw_spinlock->spinlock locking which debug code can't recognize and

>> handle.

> 

> This sounds like papering over a problem that exists somewhere else.

> 

> What I would rather make as a selling point is that raw spin locks are

> necessary to be in the RT kernel for IRQ chips.


This should be a well-known problem because other GPIO drivers also have
it.

For example this one:

https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?h=next-20201104&id=023892ec80f0efcffe22045e92bb89f3f1480f2d

Although, looking at it again, I think there is no real need to change
the dbc_lock since it doesn't relate to the IRQ. Perhaps this could be
improved in a v2.
diff mbox series

Patch

diff --git a/drivers/gpio/gpio-tegra.c b/drivers/gpio/gpio-tegra.c
index 98fc78739ebf..74a13534b9e4 100644
--- a/drivers/gpio/gpio-tegra.c
+++ b/drivers/gpio/gpio-tegra.c
@@ -61,8 +61,8 @@  struct tegra_gpio_info;
 struct tegra_gpio_bank {
 	unsigned int bank;
 	unsigned int irq;
-	spinlock_t lvl_lock[4];
-	spinlock_t dbc_lock[4];	/* Lock for updating debounce count register */
+	raw_spinlock_t lvl_lock[4];
+	raw_spinlock_t dbc_lock[4];	/* Lock for updating debounce count register */
 #ifdef CONFIG_PM_SLEEP
 	u32 cnf[4];
 	u32 out[4];
@@ -242,12 +242,12 @@  static int tegra_gpio_set_debounce(struct gpio_chip *chip, unsigned int offset,
 	/* There is only one debounce count register per port and hence
 	 * set the maximum of current and requested debounce time.
 	 */
-	spin_lock_irqsave(&bank->dbc_lock[port], flags);
+	raw_spin_lock_irqsave(&bank->dbc_lock[port], flags);
 	if (bank->dbc_cnt[port] < debounce_ms) {
 		tegra_gpio_writel(tgi, debounce_ms, GPIO_DBC_CNT(tgi, offset));
 		bank->dbc_cnt[port] = debounce_ms;
 	}
-	spin_unlock_irqrestore(&bank->dbc_lock[port], flags);
+	raw_spin_unlock_irqrestore(&bank->dbc_lock[port], flags);
 
 	tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset), offset, 1);
 
@@ -334,14 +334,14 @@  static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
 		return -EINVAL;
 	}
 
-	spin_lock_irqsave(&bank->lvl_lock[port], flags);
+	raw_spin_lock_irqsave(&bank->lvl_lock[port], flags);
 
 	val = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio));
 	val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio));
 	val |= lvl_type << GPIO_BIT(gpio);
 	tegra_gpio_writel(tgi, val, GPIO_INT_LVL(tgi, gpio));
 
-	spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
+	raw_spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
 
 	tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, gpio), gpio, 0);
 	tegra_gpio_enable(tgi, gpio);
@@ -675,8 +675,8 @@  static int tegra_gpio_probe(struct platform_device *pdev)
 						 tegra_gpio_irq_handler, bank);
 
 		for (j = 0; j < 4; j++) {
-			spin_lock_init(&bank->lvl_lock[j]);
-			spin_lock_init(&bank->dbc_lock[j]);
+			raw_spin_lock_init(&bank->lvl_lock[j]);
+			raw_spin_lock_init(&bank->dbc_lock[j]);
 		}
 	}