| Message ID | 1403199417-8833-1-git-send-email-peter.maydell@linaro.org |
|---|---|
| State | Not Applicable |
| Headers | show |
On 19 June 2014 18:36, Peter Maydell <peter.maydell@linaro.org> wrote: > target-arm queue: mostly fairly minor stuff, apart from the PSCI > patches, which have been on the list for some time. > > I meant to put this out earlier in the week but got hit by an > urgent deadline... > > thanks > -- PMM > > The following changes since commit 6baa963f4dcc211801608ebe1e0482b51653350c: > > Merge remote-tracking branch 'remotes/bonzini/scsi-next' into staging (2014-06-19 16:18:04 +0100) > > are available in the git repository at: > > > git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20140619 > > for you to fetch changes up to b6fb3a89e3cd173153f1edc4edbf970987b4ebdd: > > armv7m_nvic: fix AIRCR implementation (2014-06-19 18:33:05 +0100) > Applied, thanks. -- PMM
target-arm queue: mostly fairly minor stuff, apart from the PSCI patches, which have been on the list for some time. I meant to put this out earlier in the week but got hit by an urgent deadline... thanks -- PMM The following changes since commit 6baa963f4dcc211801608ebe1e0482b51653350c: Merge remote-tracking branch 'remotes/bonzini/scsi-next' into staging (2014-06-19 16:18:04 +0100) are available in the git repository at: git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20140619 for you to fetch changes up to b6fb3a89e3cd173153f1edc4edbf970987b4ebdd: armv7m_nvic: fix AIRCR implementation (2014-06-19 18:33:05 +0100) ---------------------------------------------------------------- target-arm: * Support PSCI 0.2 when using KVM * fix AIRCR reset value for v7M CPUs * report correct size information for pflash_cfi01 * minor coverity fixes * avoid warnings on Windows builds due to #define clash * implement TTBCR PD0/PD1 bits ---------------------------------------------------------------- Fabian Aggeler (1): target-arm: implement PD0/PD1 bits for TTBCR Oran Avraham (1): armv7m_nvic: fix AIRCR implementation Peter Maydell (6): hw/arm/spitz: Avoid clash with Windows header symbol MOD_SHIFT target-arm: Add ULL suffix to calculation of page size target-arm/translate-a64.c: Remove dead ?: in disas_simd_3same_int() target-arm/translate-a64.c: Fix dead ?: in handle_simd_shift_fpint_conv() hw/arm/vexpress: Forbid specifying flash contents in two ways at once hw/block/pflash_cfi01: Report correct size info for parallel configs Pranavkumar Sawargaonkar (6): kvm: Handle exit reason KVM_EXIT_SYSTEM_EVENT target-arm: Common kvm_arm_vcpu_init() for KVM ARM and KVM ARM64 target-arm: Enable KVM_ARM_VCPU_PSCI_0_2 feature when possible target-arm: Implement kvm_arch_reset_vcpu() for KVM ARM64 target-arm: Introduce per-CPU field for PSCI version Use PSCI v0.2 compatible string when KVM or TCG provides it hw/arm/spitz.c | 108 ++++++++++++++++++++++++--------------------- hw/arm/vexpress.c | 10 ++++- hw/arm/virt.c | 16 ++++++- hw/block/pflash_cfi01.c | 20 +++++++-- hw/intc/armv7m_nvic.c | 5 ++- kvm-all.c | 16 +++++++ target-arm/cpu-qom.h | 9 ++++ target-arm/cpu.c | 1 + target-arm/cpu.h | 16 +++++++ target-arm/helper.c | 64 +++++++++++++++++++-------- target-arm/kvm.c | 11 +++++ target-arm/kvm32.c | 16 ++++--- target-arm/kvm64.c | 26 ++++++++--- target-arm/kvm_arm.h | 12 +++++ target-arm/translate-a64.c | 5 ++- 15 files changed, 246 insertions(+), 89 deletions(-)