diff mbox

[PULL,04/14] target-arm/translate-a64.c: Remove dead ?: in disas_simd_3same_int()

Message ID 1403199417-8833-5-git-send-email-peter.maydell@linaro.org
State Accepted
Commit 220ad4ca846d8e0734dd2d2af38c61a6f5436d66
Headers show

Commit Message

Peter Maydell June 19, 2014, 5:36 p.m. UTC 
In disas_simd_3same_int(), none of the instructions permit is_q
to be false with size == 3 (this would be a vector operation with
a one-element vector, and the instruction set encodes those as
scalar operations). Replace the always-true ?: check with an
assert.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 1402171881-14343-3-git-send-email-peter.maydell@linaro.org
---
 target-arm/translate-a64.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)
diff mbox

Patch

diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 63ad787..cbc8a35 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -9052,7 +9052,8 @@  static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
     }
 
     if (size == 3) {
-        for (pass = 0; pass < (is_q ? 2 : 1); pass++) {
+        assert(is_q);
+        for (pass = 0; pass < 2; pass++) {
             TCGv_i64 tcg_op1 = tcg_temp_new_i64();
             TCGv_i64 tcg_op2 = tcg_temp_new_i64();
             TCGv_i64 tcg_res = tcg_temp_new_i64();