@@ -149,8 +149,9 @@ static u_char bch4_vector[] = {0x00, 0x6b, 0x31, 0xdd, 0x41, 0xbc, 0x10};
/* oob info generated runtime depending on ecc algorithm and layout selected */
static struct nand_ecclayout omap_oobinfo;
+static struct nand_hw_control omap_hw_controller;
+
struct omap_nand_info {
- struct nand_hw_control controller;
struct omap_nand_platform_data *pdata;
struct mtd_info mtd;
struct nand_chip nand;
@@ -1649,9 +1650,6 @@ static int omap_nand_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, info);
- spin_lock_init(&info->controller.lock);
- init_waitqueue_head(&info->controller.wq);
-
info->pdev = pdev;
info->gpmc_cs = pdata->cs;
info->reg = pdata->reg;
@@ -1672,7 +1670,13 @@ static int omap_nand_probe(struct platform_device *pdev)
info->phys_base = res->start;
- nand_chip->controller = &info->controller;
+ /*
+ * There is only one NAND controller (ECC generator) that needs to be
+ * shared among multiple devices. The NAND base driver takes care of
+ * serializing access to this single controller when multiple NAND
+ * devices are present.
+ */
+ nand_chip->hwcontrol = omap_hw_controller;
nand_chip->IO_ADDR_W = nand_chip->IO_ADDR_R;
nand_chip->cmd_ctrl = omap_hwcontrol;
There is only one NAND controller (ECC generator) that needs to be shared among multiple devices. So point nand_chip->hwcontrol to a single omap_hw_controller instance. This way the NAND base driver can take care of serializing access to this single controller (via nand_chip->controller->lock) when multiple NAND devices are present. Signed-off-by: Roger Quadros <rogerq@ti.com> --- drivers/mtd/nand/omap2.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-)