| Message ID | 20201203024423.23764-1-qiangqing.zhang@nxp.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | net: stmmac: overwrite the dma_cap.addr64 according to HW design | expand |
On Thu, 3 Dec 2020 10:44:23 +0800 Joakim Zhang wrote: > From: Fugang Duan <fugang.duan@nxp.com> > > The current IP register MAC_HW_Feature1[ADDR64] only defines > 32/40/64 bit width, but some SOCs support others like i.MX8MP > support 34 bits but it maps to 40 bits width in MAC_HW_Feature1[ADDR64]. > So overwrite dma_cap.addr64 according to HW real design. > > Signed-off-by: Fugang Duan <fugang.duan@nxp.com> > Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com> This is refactoring, not a fix, right?
> -----Original Message----- > From: Jakub Kicinski <kuba@kernel.org> > Sent: 2020年12月4日 2:42 > To: Joakim Zhang <qiangqing.zhang@nxp.com> > Cc: peppe.cavallaro@st.com; alexandre.torgue@st.com; > joabreu@synopsys.com; davem@davemloft.net; dl-linux-imx > <linux-imx@nxp.com>; netdev@vger.kernel.org > Subject: Re: [PATCH] net: stmmac: overwrite the dma_cap.addr64 according to > HW design > > On Thu, 3 Dec 2020 10:44:23 +0800 Joakim Zhang wrote: > > From: Fugang Duan <fugang.duan@nxp.com> > > > > The current IP register MAC_HW_Feature1[ADDR64] only defines > > 32/40/64 bit width, but some SOCs support others like i.MX8MP support > > 34 bits but it maps to 40 bits width in MAC_HW_Feature1[ADDR64]. > > So overwrite dma_cap.addr64 according to HW real design. > > > > Signed-off-by: Fugang Duan <fugang.duan@nxp.com> > > Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com> > > This is refactoring, not a fix, right? Hi Jakub, In theory, this is a bug fix, please let it into net repo if possible. I will add all bug fix tag for patches, and send out a V2. Thanks a lot. Best Regards, Joakim Zhang
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c index efef5476a577..223f69da7e95 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c @@ -246,13 +246,7 @@ static int imx_dwmac_probe(struct platform_device *pdev) goto err_parse_dt; } - ret = dma_set_mask_and_coherent(&pdev->dev, - DMA_BIT_MASK(dwmac->ops->addr_width)); - if (ret) { - dev_err(&pdev->dev, "DMA mask set failed\n"); - goto err_dma_mask; - } - + plat_dat->addr64 = dwmac->ops->addr_width; plat_dat->init = imx_dwmac_init; plat_dat->exit = imx_dwmac_exit; plat_dat->fix_mac_speed = imx_dwmac_fix_speed; @@ -272,7 +266,6 @@ static int imx_dwmac_probe(struct platform_device *pdev) err_dwmac_init: err_drv_probe: imx_dwmac_exit(pdev, plat_dat->bsp_priv); -err_dma_mask: err_parse_dt: err_match_data: stmmac_remove_config_dt(pdev, plat_dat); diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c index 03c6995d276a..5b1c12ff98c0 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -4975,6 +4975,14 @@ int stmmac_dvr_probe(struct device *device, dev_info(priv->device, "SPH feature enabled\n"); } + /* The current IP register MAC_HW_Feature1[ADDR64] only define + * 32/40/64 bit width, but some SOC support others like i.MX8MP + * support 34 bits but it map to 40 bits width in MAC_HW_Feature1[ADDR64]. + * So overwrite dma_cap.addr64 according to HW real design. + */ + if (priv->plat->addr64) + priv->dma_cap.addr64 = priv->plat->addr64; + if (priv->dma_cap.addr64) { ret = dma_set_mask_and_coherent(device, DMA_BIT_MASK(priv->dma_cap.addr64)); diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h index 628e28903b8b..15ca6b4167cc 100644 --- a/include/linux/stmmac.h +++ b/include/linux/stmmac.h @@ -170,6 +170,7 @@ struct plat_stmmacenet_data { int unicast_filter_entries; int tx_fifo_size; int rx_fifo_size; + u32 addr64; u32 rx_queues_to_use; u32 tx_queues_to_use; u8 rx_sched_algorithm;