diff mbox series

[v2,35/48] drm/tegra: dc: Support OPP and SoC core voltage scaling

Message ID 20201217180638.22748-36-digetx@gmail.com
State New
Headers show
Series Introduce core voltage scaling for NVIDIA Tegra20/30 SoCs | expand

Commit Message

Dmitry Osipenko Dec. 17, 2020, 6:06 p.m. UTC 
Add OPP and SoC core voltage scaling support to the display controller
driver. This is required for enabling system-wide DVFS on pre-Tegra186
SoCs.

Tested-by: Peter Geis <pgwipeout@gmail.com>
Tested-by: Nicolas Chauvet <kwizart@gmail.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
 drivers/gpu/drm/tegra/dc.c | 66 +++++++++++++++++++++++++++++++++++++-
 1 file changed, 65 insertions(+), 1 deletion(-)

Comments

Ulf Hansson Jan. 12, 2021, 2:16 p.m. UTC | #1 
- trimmed cc-list

On Thu, 17 Dec 2020 at 19:08, Dmitry Osipenko <digetx@gmail.com> wrote:
>

> Add OPP and SoC core voltage scaling support to the display controller

> driver. This is required for enabling system-wide DVFS on pre-Tegra186

> SoCs.

>

> Tested-by: Peter Geis <pgwipeout@gmail.com>

> Tested-by: Nicolas Chauvet <kwizart@gmail.com>

> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>

> ---

>  drivers/gpu/drm/tegra/dc.c | 66 +++++++++++++++++++++++++++++++++++++-

>  1 file changed, 65 insertions(+), 1 deletion(-)

>

> diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c

> index b6676f1fe358..105ad786e432 100644

> --- a/drivers/gpu/drm/tegra/dc.c

> +++ b/drivers/gpu/drm/tegra/dc.c

> @@ -11,9 +11,12 @@

>  #include <linux/interconnect.h>

>  #include <linux/module.h>

>  #include <linux/of_device.h>

> +#include <linux/pm_domain.h>

> +#include <linux/pm_opp.h>

>  #include <linux/pm_runtime.h>

>  #include <linux/reset.h>

>

> +#include <soc/tegra/common.h>

>  #include <soc/tegra/pmc.h>

>

>  #include <drm/drm_atomic.h>

> @@ -1699,6 +1702,48 @@ int tegra_dc_state_setup_clock(struct tegra_dc *dc,

>         return 0;

>  }

>

> +static void tegra_dc_update_voltage_state(struct tegra_dc *dc,

> +                                         struct tegra_dc_state *state)

> +{

> +       unsigned long rate, pstate;

> +       struct dev_pm_opp *opp;

> +       int err;

> +

> +       /* calculate actual pixel clock rate which depends on internal divider */

> +       rate = DIV_ROUND_UP(clk_get_rate(dc->clk) * 2, state->div + 2);

> +

> +       /* find suitable OPP for the rate */

> +       opp = dev_pm_opp_find_freq_ceil(dc->dev, &rate);

> +

> +       if (opp == ERR_PTR(-ERANGE))

> +               opp = dev_pm_opp_find_freq_floor(dc->dev, &rate);

> +

> +       /* -ENOENT means that this device-tree doesn't have OPP table */

> +       if (opp == ERR_PTR(-ENOENT))

> +               return;

> +

> +       if (IS_ERR(opp)) {

> +               dev_err(dc->dev, "failed to find OPP for %luHz: %pe\n",

> +                       rate, opp);

> +               return;

> +       }

> +

> +       pstate = dev_pm_opp_get_voltage(opp);

> +       dev_pm_opp_put(opp);

> +

> +       /*

> +        * The minimum core voltage depends on the pixel clock rate (which

> +        * depends on internal clock divider of the CRTC) and not on the

> +        * rate of the display controller clock. This is why we're not using

> +        * dev_pm_opp_set_rate() API and instead controlling the power domain

> +        * directly.

> +        */

> +       err = dev_pm_genpd_set_performance_state(dc->dev, pstate);


As you state above, in general we should not need to call the
dev_pm_genpd_set_performance_state() directly for the consumer driver.

Even if this looks like a special case to me, I would appreciate a
confirmation from Viresh that this is the way he also would like to
move forward from the opp library perspective.

> +       if (err)

> +               dev_err(dc->dev, "failed to set power domain state to %lu: %d\n",

> +                       pstate, err);

> +}

> +


[...]

Kind regards
Uffe
diff mbox series

Patch

diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c
index b6676f1fe358..105ad786e432 100644
--- a/drivers/gpu/drm/tegra/dc.c
+++ b/drivers/gpu/drm/tegra/dc.c
@@ -11,9 +11,12 @@ 
 #include <linux/interconnect.h>
 #include <linux/module.h>
 #include <linux/of_device.h>
+#include <linux/pm_domain.h>
+#include <linux/pm_opp.h>
 #include <linux/pm_runtime.h>
 #include <linux/reset.h>
 
+#include <soc/tegra/common.h>
 #include <soc/tegra/pmc.h>
 
 #include <drm/drm_atomic.h>
@@ -1699,6 +1702,48 @@  int tegra_dc_state_setup_clock(struct tegra_dc *dc,
 	return 0;
 }
 
+static void tegra_dc_update_voltage_state(struct tegra_dc *dc,
+					  struct tegra_dc_state *state)
+{
+	unsigned long rate, pstate;
+	struct dev_pm_opp *opp;
+	int err;
+
+	/* calculate actual pixel clock rate which depends on internal divider */
+	rate = DIV_ROUND_UP(clk_get_rate(dc->clk) * 2, state->div + 2);
+
+	/* find suitable OPP for the rate */
+	opp = dev_pm_opp_find_freq_ceil(dc->dev, &rate);
+
+	if (opp == ERR_PTR(-ERANGE))
+		opp = dev_pm_opp_find_freq_floor(dc->dev, &rate);
+
+	/* -ENOENT means that this device-tree doesn't have OPP table */
+	if (opp == ERR_PTR(-ENOENT))
+		return;
+
+	if (IS_ERR(opp)) {
+		dev_err(dc->dev, "failed to find OPP for %luHz: %pe\n",
+			rate, opp);
+		return;
+	}
+
+	pstate = dev_pm_opp_get_voltage(opp);
+	dev_pm_opp_put(opp);
+
+	/*
+	 * The minimum core voltage depends on the pixel clock rate (which
+	 * depends on internal clock divider of the CRTC) and not on the
+	 * rate of the display controller clock. This is why we're not using
+	 * dev_pm_opp_set_rate() API and instead controlling the power domain
+	 * directly.
+	 */
+	err = dev_pm_genpd_set_performance_state(dc->dev, pstate);
+	if (err)
+		dev_err(dc->dev, "failed to set power domain state to %lu: %d\n",
+			pstate, err);
+}
+
 static void tegra_dc_commit_state(struct tegra_dc *dc,
 				  struct tegra_dc_state *state)
 {
@@ -1738,6 +1783,8 @@  static void tegra_dc_commit_state(struct tegra_dc *dc,
 	if (err < 0)
 		dev_err(dc->dev, "failed to set clock %pC to %lu Hz: %d\n",
 			dc->clk, state->pclk, err);
+
+	tegra_dc_update_voltage_state(dc, state);
 }
 
 static void tegra_dc_stop(struct tegra_dc *dc)
@@ -1931,6 +1978,8 @@  static void tegra_crtc_atomic_disable(struct drm_crtc *crtc,
 	err = host1x_client_suspend(&dc->client);
 	if (err < 0)
 		dev_err(dc->dev, "failed to suspend: %d\n", err);
+
+	dev_pm_genpd_set_performance_state(dc->dev, 0);
 }
 
 static void tegra_crtc_atomic_enable(struct drm_crtc *crtc,
@@ -2523,7 +2572,6 @@  static int tegra_dc_runtime_suspend(struct host1x_client *client)
 
 	clk_disable_unprepare(dc->clk);
 	pm_runtime_put_sync(dev);
-
 	return 0;
 }
 
@@ -2881,6 +2929,18 @@  static int tegra_dc_couple(struct tegra_dc *dc)
 	return 0;
 }
 
+static int tegra_dc_init_opp_table(struct tegra_dc *dc)
+{
+	struct tegra_core_opp_params opp_params = {};
+	int err;
+
+	err = devm_tegra_core_dev_init_opp_table(dc->dev, &opp_params);
+	if (err && err != -ENODEV)
+		return err;
+
+	return 0;
+}
+
 static int tegra_dc_probe(struct platform_device *pdev)
 {
 	struct tegra_dc *dc;
@@ -2939,6 +2999,10 @@  static int tegra_dc_probe(struct platform_device *pdev)
 		tegra_powergate_power_off(dc->powergate);
 	}
 
+	err = tegra_dc_init_opp_table(dc);
+	if (err < 0)
+		return err;
+
 	dc->regs = devm_platform_ioremap_resource(pdev, 0);
 	if (IS_ERR(dc->regs))
 		return PTR_ERR(dc->regs);