| Message ID | 20201228112715.14947-3-wsa+renesas@sang-engineering.com |
|---|---|
| State | New |
| Headers | show |
| Series | v3u: add & update (H)SCIF nodes | expand |
On Mon, Dec 28, 2020 at 12:27 PM Wolfram Sang <wsa+renesas@sang-engineering.com> wrote: > SCIF0 has been enabled by the firmware, so it worked already. Still, add > the proper nodes to make it work in any case. > > Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hi Wolfram, On Tue, Jan 5, 2021 at 7:12 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > On Mon, Dec 28, 2020 at 12:27 PM Wolfram Sang > <wsa+renesas@sang-engineering.com> wrote: > > SCIF0 has been enabled by the firmware, so it worked already. Still, add > > the proper nodes to make it work in any case. > > > > Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Upon second look, this should be added to r8a779a0-falcon-cpu.dtsi, which already extends the scif0 node. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
diff --git a/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts b/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts index 0c44466d398f..54763c73dc74 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts +++ b/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts @@ -205,6 +205,9 @@ &mmc0 { }; &pfc { + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + avb0_pins: avb0 { mux { groups = "avb0_link", "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk"; @@ -348,9 +351,31 @@ mmc_pins: mmc { function = "mmc"; power-source = <1800>; }; + + scif0_pins: scif0 { + groups = "scif0_data", "scif0_ctrl"; + function = "scif0"; + }; + + scif_clk_pins: scif_clk { + groups = "scif_clk"; + function = "scif_clk"; + }; }; &rwdt { timeout-sec = <60>; status = "okay"; }; + +&scif0 { + pinctrl-0 = <&scif0_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; + status = "okay"; +}; + +&scif_clk { + clock-frequency = <24000000>; +};
SCIF0 has been enabled by the firmware, so it worked already. Still, add the proper nodes to make it work in any case. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> --- .../boot/dts/renesas/r8a779a0-falcon.dts | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+)