| Message ID | 20210111151651.1616813-8-vkoul@kernel.org |
|---|---|
| State | New |
| Headers | show |
| Series | Add and enable GPI DMA users | expand |
Hi Konrad, On 11-01-21, 17:04, Konrad Dybcio wrote: > Hi, > > looks like sdm845-cheza also uses the spi0 bus, which as far as I > understand is going to break with the GPI DMA disabled. Perhaps it > should also be enabled over there? If it is working without GPI enabled, it would work.. GPI for QUP is something that requires firmware and would have to be enabled by firmware > Actually, is there a point in disabling DMA for BLSPs/QUPs in the SoC > DTSI? I don't think any platform/vendor firmware disables entire > hosts.. Since DMA support may not be available on certain targets (firmware support), so enabling per board would make sense Thanks
On 11-01-21, 21:45, Konrad Dybcio wrote: > > > If it is working without GPI enabled, it would work.. GPI for QUP is > > something that requires firmware and would have to be enabled by > > firmware > > > I think with the new code of yours: > > > mas->tx = dma_request_slave_channel(mas->dev, "tx"); > + if (IS_ERR_OR_NULL(mas->tx)) { > + dev_err(mas->dev, "Failed to get tx DMA ch %ld", PTR_ERR(mas->tx)); ret = PTR_ERR(mas->tx); + goto out_pm; This code would be exercised *only* when DMA mode is enabled in firmware.. Both SPI and I2C driver would probe the mode supported (reason for exposing stuff in first two patches of this series).. Only if the device reports we should enable it.. Also if the device is working with FIFO mode then DMA mode wont work.. > > it *may* fail to probe with the channels assigned in the "dmas=" > property but with the engine having "status=disabled", but as I don't > have any hardware to test that driver on, please confirm whether my > concerns are right.. > > > > Since DMA support may not be available on certain targets (firmware > > support), so enabling per board would make sense > > Oh really, are there SDM845 boards shipping with GPI DMA *disabled to > all peripherals*? Is the peripheral working with FIFO mode, then answer is yes :) Thanks
diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index 7cc236575ee2..0653468f26ce 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -418,6 +418,10 @@ &gcc { <GCC_QSPI_CNOC_PERIPH_AHB_CLK>; }; +&gpi_dma0 { + status = "okay"; +}; + &gpu { zap-shader { memory-region = <&gpu_mem>; diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index c9a127bbd606..bd9952f54721 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -12,6 +12,7 @@ #include <dt-bindings/clock/qcom,lpass-sdm845.h> #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/clock/qcom,videocc-sdm845.h> +#include <dt-bindings/dma/qcom-gpi.h> #include <dt-bindings/interconnect/qcom,osm-l3.h> #include <dt-bindings/interconnect/qcom,sdm845.h> #include <dt-bindings/interrupt-controller/arm-gic.h> @@ -1183,6 +1184,9 @@ spi0: spi@880000 { interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, + <&gpi_dma0 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -2622,6 +2626,13 @@ pinmux { "gpio2", "gpio3"; function = "qup0"; }; + + config { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + drive-strength = <6>; + bias-disable; + }; }; qup_spi1_default: qup-spi1-default {
Add dmas property for spi@880000 and pinconf setting so that we can use dma for this spi device. Also, add iommu properties for qup and spi. Signed-off-by: Vinod Koul <vkoul@kernel.org> --- arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 4 ++++ arch/arm64/boot/dts/qcom/sdm845.dtsi | 11 +++++++++++ 2 files changed, 15 insertions(+)